FMS6403_08 Datasheet, PDF (5/14 Pages) Fairchild Semiconductor – Triple Video Drivers with Selectable HD/PS/SD Bypass Filters for RGB and YPbPr Signals

DC Electrical Specifications
TA=25°C, VI=1VPP, VCC=5.0V; all inputs AC coupled with 0.1µF; all outputs AC coupled into 150Ω; referenced to
400kHz; unless otherwise noted.
Symbol
ICC
VI
VIL
Parameter
Supply Current⁽²⁾
Input Voltage Maximum
Digital Input Low⁽²⁾
VIH
Digital Input High⁽²⁾
VCLAMP1 Output Clamp Voltage
VCLAMP2 Output Clamp Voltage
PSRR Power Supply Rejection Ratio
Note:
2. 100% tested at 25°C.
Conditions
VCC, no load
FSELO, FSEL1, RGB_SEL, 0dB_SEL,
EXT_SYNC, IN2_SEL, SYNC_IN
FSELO, FSEL1, RGB_SEL, 0dB_SEL,
EXT_SYNC, IN2_SEL, SYNC_IN
R,G,B,Y
Pb and Pr
DC, All Channels
Min.
0
Typ.
90
1.5
Max.
130
Units
mA
VPP
0.8
V
2.4
VCC
V
250
mV
1.125
V
-40
dB
Standard-Definition Electrical Specifications
TA=25°C, VI=1VPP, VCC=5.0V, FSEL0=0, FSEL1=0, 0dB_SEL=0 (gain=6dB), RSOURCE=37.5Ω; all inputs AC coupled with
0.1µF; all outputs AC coupled with 220µF into 150Ω referenced to 400kHz; unless otherwise noted.
Symbol
AVSD
f1dBSD
fCSD
fSBSD
dG
dφ
THD
XTALK
INMUXISO
Parameter
SD Gain, 0dB_SEL=0⁽³⁾
SD Gain, 0dB_SEL=1⁽³⁾
-1dB Bandwidth for SD
-3dB Bandwidth for SD
Attenuation: SD (Stop-band
Rejection)⁽³⁾
Differential Gain
Differential Phase
Output Distortion,
All Channels
Crosstalk, Channel-to-channel
INMUX Isolation
SNR Signal-to-Noise Ratio
tpdSD
Propagation Delay for SD
T1
SYNC to SYNC_IN Delay
T2
SYNC_IN Minimum Pulse
Width
Note:
3. 100% tested at 25°C.
Conditions
All Channels, SD Mode
All Channels
All Channels
All Channels at f=27MHz
All Channels
All Channels
VOUT=1.8VPP at 1MHz
At 1.0MHz
At 1.0MHz
All Channels, NTC-7 Weighting,
4.2MHz Lowpass, 100Khz Highpass
Delay from Input to Output at
4.5MHz
Min.
5.6
-0.4
5.5
40
Typ.
6.0
0
7.6
8.5
56
0.40
0.25
0.4
-68
-70
74
80
10
4
Max.
6.4
0.4
Units
dB
MHz
MHz
dB
%
°
%
dB
dB
dB
ns
ns
µs
© 2005 Fairchild Semiconductor Corporation
FMS6403 • Rev. 1.0.4
5
www.fairchildsemi.com