FDS2572 Datasheet, PDF (9/12 Pages) Fairchild Semiconductor – 150V, 0.047 Ohms, 4.9A, N-Channel UltraFET Trench MOSFET

SABER Electrical Model
REV August 2001
template FDS2572 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=4e-11,nl=1.131,rs=4.4e-3,trs1=2e-3,trs2=1e-6,cjo=1.44e-9,m=0.67,tt=7.4e-8,xti=4.2)
dp..model dbreakmod = (rs=0.38,trs1=2e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=5e-10,isl=10e-30,nl=10,m=0.7)
m..model mstrongmod = (type=_n,vto=4.05,kp=85,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=3.35,kp=5,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.76,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-10,voff=-2)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-10)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.3)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.8)
c.ca n12 n8 = 8e-10
c.cb n15 n14 = 8e-10
c.cin n6 n8 = 2e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
DPLCAP ₅
10
RSLC2
RSLC1
51
ISCL
-
50
DBREAK
LDRAIN
DRAIN
2
RLDRAIN
spe.ebreak n11 n7 n17 n18 = 157.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
GATE
1
ESG
6
8
RDRAIN
+
EVTHRES
16
+ ₁₉ - 21
LGATE
EVTEMP
8
RGATE _{+ 18 - 6}
9
20 ²²
MMED
RLGATE
MSTRO
CIN
8
11
MWEAK
EBREAK
+
17
18
-
7
DBODY
LSOURCE
SOURCE
3
l.lgate n1 n9 = 5.61e-9
RSOURCE
RLSOURCE
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1.98e-9
S1A
12 ₁₃
8
S2A
14
15
13
RBREAK
17
18
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
CA
res.rlsource n3 n7 = 19.8
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
S1B
S2B
13
CB
+
+ ¹⁴
EGS
6
8
-
EDS
5
8
-
RVTEMP
19
IT
-
VBAT
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-3e-7
res.rdrain n50 n16 = 2.1e-2, tc1=1e-2,tc2=3e-5
res.rgate n9 n20 = 1.47
res.rslc1 n5 n51 = 1e-6, tc1=3e-3,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.5e-2, tc1=4.5e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-3e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-5e-3,tc2=2e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/65))** 3))
}
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. B, October 2001