GTLP16616 Datasheet, PDF (8/10 Pages) Fairchild Semiconductor – 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

Test Circuits and Timing Waveforms
Test Circuit for A Outputs
Test Circuit for B Outputs
C_L includes probes and jig capacitance.
C_L includes probes and jig capacitance.
For B-Port outputs, C_L = 30 pF is used for worst case
edge rate.
Voltage Waveforms Pulse Duration
(Vm = 1.5V for A-Port and 1.0V for B-Port)
Voltage Waveforms Propagation Delay and Setup and Hold Times
(Vm = 1.5V for A-Port and 1.0V for B-Port)
Voltage Waveforms Enable and Disable Times (A-Port)
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is high except when disabled by the output control. All input pulses have the following characteristics: frequency = 10
MHz, t_r = t_f = 2 ns, Z_O = 50Ω. The outputs are measured one at a time with one transition per measurement.
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