GTLP16616 Datasheet, PDF(2/10 Page) Fairchild Semiconductor – 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

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GTLP16616 Datasheet, PDF (2/10 Pages) Fairchild Semiconductor – 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

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Pin Descriptions

Pin Names

OEAB

OEBA

CEAB

CEBA

LEAB

LEBA

VREF

CLKAB

CLKBA

A1-A17

B1-B17

CLKIN

CLKOUT

Description

A-to-B Output Enable (Active LOW)

B-to-A Output Enable (Active LOW)

A-to-B Clock Enable (Active LOW)

B-to-A Clock Enable (Active LOW)

A-to-B Latch Enable (Transparent HIGH)

B-to-A Latch Enable (Transparent HIGH)

GTLP Reference Voltage

A-to-B Clock

B-to-A Clock

A-to-B Data Inputs or B-to-A 3-STATE

Outputs

B-to-A Data Inputs or

A-to-B Open Drain Outputs

B-to-A Buffered Clock Output

GTLP Buffered Clock Output of CLKAB

Connection Diagram

Functional Description

The GTLP16616 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for

the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock

enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and

OEBA). The clock enables (CEAB and CEBA) enable all 17 bits. The output enables (OEAB and OEBA) control both the 17

bits of data and the CLKOUT/CLKIN buffered clock path.

For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop

and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is

latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When

OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is

similar except that CEBA, OEBA, LEBA and CLKBA are used.

Truth Table

(Note 1)

Inputs

CEAB OEAB LEAB CLKAB

H or L

Output

B0 (Note 2)

B0 (Note 3)

Mode

Latched

storage

of A data

Transparent

Clocked storage

of A data

Clock inhibit

Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.

Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH prior to LEAB going LOW.

Note 3: Output level before the indicated steady-state input conditions were established.

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