FXMA2102 Datasheet, PDF (7/16 Pages) Fairchild Semiconductor – Dual Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications

Buffer / Repeater Performance
The FXMA2102 dynamic drivers have enough current
sourcing capability to drive a 400 pF capacitive bus.
This is beneficial for instances when an I²C buffer /
repeater is required. The I²C specification stipulates a
maximum bus capacitance of 400 pF. If an I²C segment
exceeds 400 pF, an I²C buffer / repeater is required to
split the segment into two segments, each of which is
less than 400 pF. Figure 5 is a scope shot of an
FXMA2102 driving a lumped load of 600 pF. Notice the
(30% - 70%) rise time is only 112 ns (R_PU = 2.2 K). This
is well below the maximum edge rate of 300 ns. Not only
does the FXMA2102 drive 400 pF, but it also provides
excellent headroom below the I²C specification
maximum edge rate of 300 ns.
V_OL vs. I_OL
The I²C specification mandates a maximum V_IL (I_OL of
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V_CC of 3.3 V, the maximum V_IL of the master is (1.65 V x
0.3) 495 mV. The slave could legally transmit a valid
logic LOW of 0.4 V to the master.
If the I²C translator’s channel resistance is too high, the
voltage drop across the translator could present a V_IL to
the master greater than 495 mV. To complicate matters,
the I²C specification states that 6 mA of I_OL is
recommended for bus capacitances approaching
400
I²C
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across
when
the
I²C
translators exhibit low V_OL performance. Figure 6 depicts
typical FXMA2102 V_OL performance vs. the competition,
given a 0.4 V V_IL.
Figure 6. V_OL vs. I_OL
© 2010 Fairchild Semiconductor Corporation
FXMA2102 • Rev. 1.0.5
7
www.fairchildsemi.com