FAN7389 Datasheet, PDF (7/18 Pages) Fairchild Semiconductor – 3-Phase Half-Bridge Gate-Drive IC

Electrical Characteristics
VBIAS (VDD, VBS1,2,3) = 15.0V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to
COM and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM and are
applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to COM. The
VBSUV parameters are referenced to VS1,2,3.
Symbol
Parameter
Conditions
Over-Current Protection Section
VCSTH+ Over-Current Detect Positive Threshold⁽⁵⁾
VCSTH- Over-Current Detect Negative Threshold⁽⁵⁾
VCSHYS Over-Current Detect Hysteresis⁽⁵⁾
ICSIN Short-Circuit Input Current
ISOFT Soft Turn-Off Sink Current
Fault Output Section
VRCINTH+ RCIN Positive-Going Threshold Voltage
VRCINTH- RCIN Negative-Going Threshold Voltage
VRCINHYS RCIN Hysteresis Voltage
IRCIN RCIN Internal Current Source
VFOL Fault Output Low Level Voltage
RDSRCIN RCIN On Resistance
RDSFO Fault Output On Resistance
Note:
5. These parameters are guaranteed by design.
VCSIN=1V
CRCIN=2nF
VCS=1V, IFO=1.5mA
IRCIN=1.5mA
IFO=1.5mA
Min. Typ. Max. Unit
400 500 600 mV
440
mV
60
mV
5 10 15 μA
25 40 55 mA
3.3
V
2.6
V
0.7
V
3
5
7 µA
0.2 0.5 V
50 75 100 Ω
90 130 170 Ω
Dynamic Electrical Characteristics
TA=25°C, VBIAS (VDD, VBS1,2,3) = 15.0V, VS1,2,3 = COM, and CLoad = 1000pF unless otherwise specified.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
tON Turn-On Propagation Delay
VLIN1,2,3=VHIN1,2,3=0V, VS1,2,3=0V
350 500 650
ns
tOFF Turn-Off Propagation Delay
VLIN1,2,3=VHIN1,2,3=5V, VS1,2,3=0V
350 500 650
ns
tR Turn-On Rise Time
VLIN1,2,3=VHIN1,2,3=0V
20 50 100 ns
tF Turn-Off Fall Time
VLIN1,2,3=VHIN1,2,3=5V
10 30 80 ns
tEN Enable LOW to Output Shutdown Delay
tCSBLT CS Pin Leading-Edge Blanking Time⁽⁶⁾
400 500 600 ns
200 300 400 ns
tCSFO _{Time from CS Triggering to} FO
From VCSC=1V to FO Turn-Off
630
ns
tCSOFF
tFLT,IN
Time from CS Triggering to All Gate
Outputs Turn-Off
Input Filtering Time⁽⁷⁾ (HINx, LINx)
Input Filtering Time⁽⁷⁾ (EN)
From VCSC=1V to Starting Gate
Turn-Off
640
ns
200 250 300 ns
200 250 300 ns
tFLTCLR Fault-Clear Time
DT Dead Time
RCIN: CRCIN=2nF
1.3
ms
250 300 350 ns
MDT Dead-Time Matching (All Six Channels)
50 ns
MT Delay Matching (All Six Channels)
50 ns
PM Output Pulse-Width Matching^(6,8)
PWIN > 1µs
50 100 ns
Notes:
6. These parameters are guaranteed by design.
7. The minimum width of the input pulse should exceed 500ns to ensure the filtering time of the input filter is exceeded.
8. PM is defined as PWIN-PWOUT,
© 2010 Fairchild Semiconductor Corporation
FAN7389 • Rev. 1.0.0
7
www.fairchildsemi.com