FAN7389 Datasheet, PDF (14/18 Pages) Fairchild Semiconductor – 3-Phase Half-Bridge Gate-Drive IC

Applications Information
1. Dead Time
Dead time is automatically inserted whenever the dead
time of the external two input signals (between HINx
and LINx signals) is shorter than internal fixed dead
times (DT1 and DT2). Otherwise, external dead times
larger than internal dead times are not modified by the
gate driver and internal dead-time waveform definition is
shown in Figure 37.
2.2 Shoot-Through Protection
The shoot-through protection circuitry prevents both
high- and low-side switches from conducting at the
same time, as shown Figure 39.
Figure 37.Internal Dead-Time Definitions
2. Protection Function
2.1 Fault Out ( _FO ) and Under-Voltage Lockout
The high- and low-side drivers include under-voltage
lockout (UVLO) protection circuitry that monitors the
supply voltage for VDD and VBS independently. It can be
designed to prevent malfunction when VDD and VBS are
lower than the specified threshold voltage. Also, the
UVLO hysteresis prevents chattering during power-
supply transitions. Moreover, the fault signal ( _FO ) goes
to LOW state to operate reliably during power-on
events, when the power supply (VDD) is below the
under-voltage lockout high threshold voltage for the
circuit (during t1 ~ t2). The UVLO circuit is not otherwise
activated; shown Figure 38.
Figure 39.Shoot-Through Protection
2.3 Enable Input
When the EN pin is in HIGH state, the gate driver
operates normally. When a condition occurs that should
shut down the gate driver, the EN pin should be LOW.
The enable circuitry has an input filter; the minimum
input duration is specified by tFLT,IN (typically 250ns).
Figure 38.Waveforms for Under-Voltage Lockout
Figure 40.Output Enable Timing Waveform
© 2010 Fairchild Semiconductor Corporation
FAN7389 • Rev. 1.0.0
14
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