FOD8012 Datasheet, PDF (6/12 Pages) Fairchild Semiconductor – High CMR, Bi-Directional, Logic Gate Optocoupler

Typical Performance Curves (Continued)
Fig. 7 Typical Propagation Delay vs. Output Load
Capacitance (Channel A & B)
45
Frequency = 7.5MHz
Duty Cycle = 50%
V_DD1 = V_DD2 = 3.3V
43
t_PLH
41
t_PHL
39
37
35
15
20
25
30
35
40
45
50
55
CL – OUTPUT LOAD CAPACITANCE (pF)
Fig. 9 Typical Rise Time vs. Output Load Capacitance
(Channel A & B)
12
Frequency = 7.5MHz
Duty Cycle = 50%
V_DD1 = V_DD2 = 3.3V
10
8
t_R
6
4
2
15
20
25
30
35
40
45
50
55
CL – OUTPUT LOAD CAPACITANCE (pF)
Fig. 8 Typical tPHL – tPLH vs. Output Load Capacitance
(Channel A & B)
0
Frequency = 7.5MHz
Duty Cycle = 50%
V_DD1 = V_DD2 = 3.3V
-1
-2
-3
-4
-5
15
20
25
30
35
40
45
50
55
CL – OUTPUT LOAD CAPACITANCE (pF)
Fig. 10 Typical Fall Time vs. Output Load Capacitance
(Channel A & B)
16
Frequency = 7.5MHz
Duty Cycle = 50%
V_DD1 = V_DD2 = 3.3V
14
12
t_F
10
8
6
4
15
20
25
30
35
40
45
50
55
CL – OUTPUT LOAD CAPACITANCE (pF)
©2010 Fairchild Semiconductor Corporation
FOD8012 Rev. 1.0.5
6
www.fairchildsemi.com