9034 Datasheet, PDF (6/7 Pages) Fairchild Semiconductor – Power MOSFET Avalanche Guideline

Assume a situation where the drain-source voltage of a Power MOSFET applied to a switching
power supply exceeds its maximum rating specified in the datasheet during delay time to pro-
tection activation while conducting short circuit test. The specific conditions are as follows:
FQA9N90C switching device, 100ns t_AV, 9.2µs period, and 20ms delay time. In this case, the
transient thermal resistance becomes
Z_ΘJC(t) = 0.01 × Z_ΘJC(20ms) + (1 – 0.01) ×
Z_ΘJC(9.3µs) + Z_ΘJC(100ns) – Z_ΘJC(9.2µs) = 0.00274
If a 5kW power loss is assumed during avalanche, the resulting junction temperature rise will
be
∆T = 5kW × 0.00274°C ⁄ W = 13.7°C
This is an additional junction temperature rise caused by avalanche. Therefore, the system
designer should first calculate the junction temperature of a normal operation, and then add
the above value to obtain the transient junction temperature during avalanche. This tempera-
ture should be kept below the maximum allowable junction temperature with some safety mar-
gin according to the designer’s choice.
5. Conclusions
The system designers are frequently forced to determine the applicability of a Power MOSFET
to their application. This can be done by using the avalanche mode analysis and/or junction
temperature analysis which are very practical.
References
[1] “Single Pulse Unclamped Inductive Switching: A Rating System”, Fairchild Application Note
AN-7514
[2] “A Combined Single Pulse and Repetitive UIS Rating System”, Fairchild Application Note
AN-7515
[3] Rudy Severns, 1984, “Safe Operating Area and Thermal Design for MOSPOWER
Transistors”, MOSPOWER Applications Handbook, Siliconix
©2004 Fairchild Semiconductor Corporation
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Rev. A, March 2004