9034 Datasheet, PDF (2/7 Pages) Fairchild Semiconductor – Power MOSFET Avalanche Guideline

2. Over-Voltage Conditions
The over-voltage conditions in actual applications can be classified into two different groups.
One is when the drain-source voltage of Power MOSFET exceeds the specified absolute max-
imum rating but is still short of the breakdown voltage of the device. This is not an avalanche
situation and the device feasibility can be determined through junction temperature analysis.
Another is when the device breaks down and goes into avalanche mode. The Rating System
is a great tool for avalanche mode analysis.
3. Avalanche Mode Analysis
When the Power MOSFET avalanches, the drain-source voltage is clamped to its effective
breakdown voltage and the current is commutated through a parasitic antiparallel diode. Fig-
ure 2 shows typical avalanche waveforms in switching power supplies. The drain-source volt-
age is over 1kV and a commutating current is observed.
Figure 2. Device Breakdown, 800V Rated MOSFET
The UIS Rating System is very useful in dealing with avalanche situations. There are three
areas in the UIS SOA graph as indicated in Figure 3 : (1) above and right of the 25°C line, (2)
below and left of the maximum junction temperature line, (3) in between the two lines. (1) and
(2) are easy to determine: the device is within the UIS rating ((2)), or beyond the rating ((1)).
But the junction temperature of the Power MOSFET at the start of the UIS pulse is required to
determine (3). The junction temperature analysis methods will be discussed later in detail.
This UIS Rating System can also be applied to repetitive pulses through superposition tech-
nique. Each UIS pulse is evaluated separately just as in single pulse. Usually, the last pulse
in a series of power pulses occurs at the highest junction temperature and is therefore the
worst stress. If the Power MOSFET is within the specified UIS rating for the last pulse, it is
certainly within the UIS ratings for previous pulses which occurred at a lower junction temper-
ature.^[2]
©2004 Fairchild Semiconductor Corporation
100
(2)
10
(1)
STARTING T = 25 oC
J
(3)
STARTING T = 150 oC
J
1
0.01
0.1
1
10
100
t , TIME IN AVALANCHE (ms)
AV
Figure 3. UIS Capability, FDP050AN06A0
2
Rev. A, March 2004