FIN1049 Datasheet, PDF (5/10 Pages) Fairchild Semiconductor – LVDS Dual Line Driver with Dual Line Receiver

Required Specifications
1. Human Body Model ESD and Machine Model ESD
should be measured using MIL-STD-883C method
3015.7 standard.
2. Latch-up immunity should be tested to the EIA/JEDEC
Standard Number 78 (EIA/JESD78).
Note: C_L = 15pF, includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
V_IA
1.25
1.15
V_CC
V_CC - 0.1
0.1
0.0
1.75
0.65
V_CC
V_CC - 1.1
1.1
0.0
V_IB
1.15
1.25
V_CC - 0.1
V_CC
0.0
0.1
0.65
1.75
V_CC - 1.1
V_CC
0.0
1.1
Resulting Differential Input
Voltage (mV)
V_ID
100
−100
100
−100
100
−100
1100
−1100
1100
−1100
1100
−1100
Resulting Common
Mode Input Voltage (V)
V_IC
1.2
1.2
V_CC - 0.05
V_CC - 0.05
0.05
0.05
1.2
1.2
V_CC - 0.55
V_CC - 0.55
0.55
0.55
Note: R_L = 100Ω
FIGURE 2. LVDS Output Circuit for DC Test
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