FIN1049 Datasheet, PDF (4/10 Pages) Fairchild Semiconductor – LVDS Dual Line Driver with Dual Line Receiver

AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 5)
Switching Characteristics - LVDS Outputs
t_PLHD
Differential Propagation Delay LOW-to-HIGH
t_PHLD
Differential Propagation Delay HIGH-to-LOW
t_TLHD
Differential Output Rise Time (20% to 80%)
0.2
t_THLD
Differential Output Fall Time (80% to 20%)
See Figures 3, 4
0.2
t_SK(P)
Pulse Skew |t_PLH - t_PHL|
t_SK(LH),
Channel-to-Channel Skew (Note 6)
t_SK(HL)
t_SK(PP)
Part-to-Part Skew (Note 7)
t_PZHD
Differential Output Enable Time from Z-to-HIGH
t_PZLD
t_PHZD
Differential Output Enable Time from A-to-LOW
See Figures 5, 6
Differential Output Disable Time from HIGH-to-Z
t_PLZD
Differential Output Disable Time from LOW-to-Z
f_MAXD
Maximum Frequency (Note 8)
See Figure 3
200
Switching Characteristics - LVTTL Outputs
2.0
ns
2.0
ns
1.0
ns
1.0
ns
0.35
ns
0.35
ns
1.0
ns
6.0
ns
6.0
ns
3.0
ns
3.0
ns
MHz
t_PHL
Propagation Delay HIGH-to-LOW
Measured from 20% to 80% signal
0.5
1.0
3.5
t_PLH
Propagation Delay LOW-to-HIGH
V_ID = 200mV;
0.5
1.0
3.5
t_SK1
Pulse Skew
Distributed Load
0.0
35.0
400
t_SK2
Channel-to-Channel Skew
C_L = 15pF and 50Ω;
0.0
50.0
500
t_SK3
Part-to-Part Skew
R_L = 1KΩ;
0.0
1.0
t_LHR
Transition Time LOW-to-HIGH
V_OS = 1.2V;
0.1
0.25
1.4
t_HLR
Transition Time HIGH-to-LOW
See Figures 7, 8
0.1
0.18
1.4
t_PHZ
Disable Time HIGH-to-Z
2.2
4.5
8.0
t_PLZ
Disable Time LOW-to-Z
t_PZH
Enable Time Z-to-HIGH
See Figures 9, 10
1.3
3.5
8.0
1.8
3.0
7.0
t_PZL
Enable Time Z-to-LOW
0.9
1.4
7.0
f_MAXT
Maximum Frequency (Note 9)
See Figure 7
200
Note 5: All typical values are at T_A = 25°C and with V_CC = 3.3V.
Note 6: t_SK(LH), t_SK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same
direction.
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
MHz
Note 7: t_SK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 8: f_MAX generator input conditions: t_r = t_f < 1ns (10% to 90%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45% / 55%, V_OD > 250mV, all chan-
nels switch.
Note 9: f_MAXT generator input conditions: t_r = t_f < 1ns (10% to 90%), 50% duty cycle, V_ID = 200mV, V_CM = 1.2V. Output criteria: duty cycle = 45% / 55%, V_OH
> 2.7V. V_OL < 0.25V, all channels switching.
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