FOD2200_08 Datasheet, PDF (4/11 Pages) Fairchild Semiconductor – Low Input Current Logic Gate Optocouplers

Electrical Characteristics (Continued)
Transfer Characteristics (T_A = 0°C to +85°C, V_CC = 4.5V to 20V, I_F(ON) = 1.6mA to 5mA, V_EH = 2V to 20V,
V_EL = 0V to 0.8V, I_F(OFF) = 0mA to 0.1mA unless otherwise specified.)⁽¹⁾
Symbol DC Characteristics
Test Conditions
Min. Typ.* Max. Unit
I_OHH
Output Leakage Current
(V_OUT > V_CC)
V_CC = 4.5V, I_F = 5mA V_O = 5.5V
V_O = 20V
2.0
100
µA
2.5
500
V_OL Low Level Output Voltage V_CC = 4.5 V, I_F = 0mA, V_E = 0.4 V,
I_OL = 6.4mA⁽²⁾
0.33
0.5
V
I_FT Input Threshold Current
V_CC = 4.5V, V_O = 0.5V, V_E = 0.4V,
I_OL = 6.4mA
1.6
mA
V_OH Logic High Output Voltage I_OH = -2.6mA
2.4 V_CC – 1.8
V
I_OZL High Impedance State
Output Current
V_O = 0.4V, V_EN = 2V, I_F = 5mA
-20
µA
I_OZH
High Impedance State
Output Current
V_O = 2.4 V, V_EN = 2 V, I_F = 5mA
V_O = 5.5 V, V_EN = 2 V, I_F = 5mA
20
µA
100
V_O = 20 V, V_EN = 2 V, I_F = 5mA
500
I_OSL Logic Low Short Circuit
V_O = V_CC = 5.5V, I_F = 0mA
25
mA
Output Current⁽¹⁰⁾
V_O = V_CC = 20V, I_F = 0mA
40
I_OSH Logic High Short Circuit
V_CC = 5.5V, I_F = 5mA, V_O = GND
-10
mA
Output Current⁽¹⁰⁾
V_CC = 20V, I_F = 5mA, V_O = GND
-25
I_HYS Input Current Hysteresis V_CC = 4.5V
0.03
mA
Isolation Characteristics (T_A = 0°C to +85°C unless otherwise specified)
Symbol
Characteristics
V_ISO
R_I-O
C_I-O
Withstand Insulation Test Voltage
Resistance (Input to Output)
Capacitance (Input to Output)
Test Conditions
R_H < 50%, T_A = 25°C, t = 1 min.⁽⁹⁾
V_I-O = 500 VDC⁽⁹⁾
V_I-O = 0V, f = 1MHz⁽⁹⁾
Min.
5000
Typ.*
10¹²
0.6
Max.
Unit
V_RMS
Ω
pF
*Typical values at T_A = 25°C, V_CC = 5V, I_F(ON) = 3mA unless otherwise stated.
Notes:
1. The V_CC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package V_CC and GND pins of each device.
2. t_PLH – Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse
to the 1.3V level on the LOW to HIGH transition of the output voltage pulse.
3. t_PHL – Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse
to the 1.3V level on the HIGH to LOW transition of the output voltage pulse.
4. When the peaking capacitor is omitted, propagation delay times may increase by 100ns.
5. t_r – Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse.
6. t_f – Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse.
7. CM_H – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high
state (i.e., V_OUT > 2.0V).
8. CM_L – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low
state (i.e., V_OUT < 0.8V).
9. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted together.
10. Duration of output short circuit time should not exceed 10ms.
©2004 Fairchild Semiconductor Corporation
FOD2200 Rev. 1.0.1
4
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