GTLP16T1655 Datasheet, PDF (3/14 Pages) Fairchild Semiconductor – 16-Bit LVTTL/GTLP Universal Bus Transceiver

Functional Description
The GTLP16T1655 is a high drive (100 mA) 16-bit univer-
sal bus transceiver containing D-type flip-flop, latch and
transparent modes of operation for the data path. The
device is uniquely partitioned as two 8-bit transceivers with
individual latch timing and output control signals but with a
common clock pin (CLK) for both transceiver words. Data
flow for each word is determined by the respective latch
enables (xLEAB and xLEBA), output enables (xOEAB and
xOEBA) and clock (CLK). The output enables (1OEAB,
1OEBA, and 2OEAB and 2OEBA) control Byte1 and Byte2
data for the A to B and B to A directions respectively.
Logic Diagrams
For A-to-B data flow, the devices operate in the transparent
mode when LEAB is HIGH. When LEAB transitions LOW,
the A data is latched independent of CLK HIGH or LOW. If
LEAB is LOW the A data is registered on the CLK LOW-to-
HIGH transition. When OEAB is LOW the outputs are
active. With OEAB HIGH the outputs are HIGH impedance.
Data flow for the B-to-A direction is identical but uses
OEBA, LEBA and CLK. Note that CLK is common to both
directions and both 8-bit words. OE is also common and is
used to disable all I/O ports simultaneously.
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