GTLP16T1655 Datasheet, PDF (2/14 Pages) Fairchild Semiconductor – 16-Bit LVTTL/GTLP Universal Bus Transceiver

Connection Diagram
Pin Descriptions
Pin Names
Description
1OEAB
A-to-B Output Enable (Active LOW)
2OEAB
Byte 1 and Byte 2
1OEBA
B-to-A Output Enable (Active LOW)
2OEBA
Byte 1 and Byte 2
OE
Disables all I/O ports simultaneously
1LEAB
A-to-B Latch Enable (Transparent HIGH)
2LEAB
Byte 1 and Byte 2
1LEBA
B-to-A Latch Enable (Transparent HIGH)
2LEBA
Byte 1 and Byte 2
V_REF
CLK
GTLP Reference Voltage
A-to-B and B-to-A Clock
1A1-1A8
A Port I/O Byte 1 and Byte 2
2A1-2A8
1B1-1B8
B Port I/O Byte 1 and Byte 2
2B1-2B8
Truth Tables
(Note 1)
CEAB
H
L
L
L
L
L
L
Inputs
LEAB
X
H
H
L
L
L
L
CLK
X
X
X
↑
↑
H
L
Output
A
B
Mode
X
Z
High Impedance
L
L
Transparent
H
H
Transparent
L
L
Registered
H
H
Registered
X
B₀ (Note 2)
Previous State
X
B₀ (Note 3)
Previous State
Inputs
OE
L
L
L
L
H
OEAB
L
L
H
H
X
OEBA
L
H
L
H
X
Outputs
A Port
Active
Z
Active
Z
Z
B Port
Active
Active
Z
Z
Z
Inputs
V_ERC
V_CC
GND
Output Edge
B Port
Slow
Fast
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLK.
Note 2: Output level before the indicated steady state input conditions were established, provided CLK was HIGH prior to LEAB going LOW.
Note 3: Output level before the indicated steady state input conditions were established.
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