FAN5109B Datasheet, PDF (3/14 Pages) Fairchild Semiconductor – Dual Bootstrapped 12V MOSFET Driver

Pin Configuration
BOOT
PWM
OD
VCC
1
8
2 FAN 7
3 ⁵⁰⁰⁹ 6
4
5
HDRV
SW
PGND
LDRV
Figure 3. Pin Assignments
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
Name
BOOT
PWM
OD
VCC
LDRV
PGND
SW
HDRV
Description
Bootstrap Supply Input. Provides voltage supply to the high-side MOSFET driver. Connect
to the bootstrap capacitor (see the Applications section).
PWM Signal Input. This pin accepts a logic-level PWM signal from the controller.
Output Disable. When LOW, this pin disables FET switching (HDRV and LDRV are held
LOW). (Also referred to as OD#.)
Power Input. +12V chip bias power. Bypass with a 1μF ceramic capacitor.
Low-Side Gate Drive Output. Connect to the gate of low-side power MOSFET(s).
Power ground. Connect directly to the source of the low-side MOSFET(s).
Switch Node Input. Connect as shown in Figure 1. SW provides return for the high-side
bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.
High-Side Gate Drive Output. Connect to the gate of high-side power MOSFET(s).
© 2006 Fairchild Semiconductor Corporation
FAN5109B Rev. 1.0.0
3 of 14
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