FAN5109B Datasheet, PDF (11/14 Pages) Fairchild Semiconductor – Dual Bootstrapped 12V MOSFET Driver

Application Information
Supply Capacitor Selection
To reduce the noise and to supply the peak current, a
local ceramic bypass capacitor is recommended for the
supply input (VCC). Use at least a 1μF, X7R or X5R
capacitor. Keep this capacitor close to the VCC and
PGND pins.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBOOT) and an external diode, as shown in Figure 1.
These components should be selected after the high-
side MOSFET has been chosen. The required
capacitance is determined using the following equation:
C_BOOT =
Q_G
ΔV_BOOT
EQ. 1
where QG is the total gate charge of the high-side
MOSFET and ΔVBOOT is the voltage droop allowed on
the high-side MOSFET drive. For example, the QG of a
FDD6696 MOSFET is about 35nC at 12VGS. For an
allowed droop of ~300mV, the required bootstrap
capacitance is 100nF. A good quality ceramic capacitor
must be used. The average diode forward current,
IF(AVG), can be estimated by:
I_F(AVG) = Q_GATE × F_SW
EQ. 2
where FSW is the switching frequency of the controller.
The peak surge current rating of the diode should be
checked in-circuit, since this is dependent on the
equivalent impedance of the entire bootstrap circuit,
including the PCB traces.
Thermal Considerations
Total device dissipation:
P_Dtot = P_Q + P_HDRV + P_LDRV
EQ. 3
where:
• PQ represents quiescent power
P_Q = V_CC × [4mA + 0.036 (F_SW − 100)]
dissipation:
EQ. 4
• FSW is switching frequency (in kHz).
• PHDRV represents internal power dissipation of the
upper FET driver.
• PH(R) and PH(F) are internal dissipations for the rising
and falling edges, respectively:
P_HDRV = P_H(R) + P_H(F)
EQ. 5
P_H(R)
= P_Q1 ×
R_HUP
R_HUP + R_E
+ R_G
EQ. 6
P_H(F)
= P_Q1 ×
R_HDN
R_HDN + R_E + R_G
EQ. 7
P_Q1
=
1
2
×
Q_G1
×
V_GS(Q1)
× F_SW
EQ. 8
where:
• QG1 is total gate charge of the upper FET (Q1) for
its applied VGS.
As described in Equations 6 and 7, the total power
consumed driving the gate is divided in proportion to the
resistances in series with the MOSFET internal gate
node, as shown below:
BOOT
R_HUP
HDRV
Q1
R_E
R_G
G
R_HDN
S
SW
Figure 20. Driver Dissipation Model
RG is the gate resistance internal to the FET. RE is the
external gate drive resistor implemented in many
designs. Note that the introduction of RE can reduce
driver power dissipation, but excess RE may cause
errors in the “adaptive gate drive” circuitry. In particular,
adding RE in the low drive circuit could result in shoot
through. For more information, refer to Application Note
AN-6003, "Shoot-through" in Synchronous Buck Converters.
PLDRV is dissipation of the lower FET driver:
P_LDRV = P_L(R) + P_L(F)
EQ. 9
where:
PL(R) and PL(F) are internal dissipations for the rising
and falling edges, respectively:
P_L(R)
= P_Q2
×
R_LUP
R_LUP + R_E
+ R_G
EQ. 10
P_L(F)
= P_Q2
×
R_LDN
R_HDN + R_E
+ R_G
EQ. 11
P_Q2
=
1
2
×
Q
G2
× V_GS(Q2)
× F_SW
EQ. 12
© 2006 Fairchild Semiconductor Corporation
FAN5109B Rev. 1.0.0
11 of 14
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