FAN5109B Datasheet, PDF (10/14 Pages) Fairchild Semiconductor – Dual Bootstrapped 12V MOSFET Driver

Circuit Description
The FAN5109B is optimized for driving N-channel
MOSFETs in a synchronous buck converter topology. A
single PWM input signal is all that is required to
properly drive the high-side and low-side MOSFETs.
For a more detailed description of the FAN5109B and
its features, refer to the Typical Application diagram in
Figure 1 and Functional Block diagram in Figure 2.
Low-Side Driver ( ^OD = HIGH)
The FAN5109B low-side driver (LDRV) is designed to drive
ground-referenced, N-channel MOSFETs. The bias for
LDRV is internally connected between VCC and PGND.
When the driver is enabled, the driver LDRV output is 180°
out of phase with the PWM input. When the FAN5109B is
disabled ( OD =LOW), LDRV is held LOW.
High-Side Driver ( ^OD = HIGH)
The FAN5109B high-side driver (HDRV) is designed to
drive a floating N-channel MOSFET. The bias voltage
for the high-side driver is developed by a bootstrap
supply circuit, consisting of an external diode and
bootstrap capacitor (CBOOT).
During start-up, SW is initially at PGND, allowing CBOOT
to charge to VCC through the external boot diode. When
the PWM input goes HIGH, HDRV begins to charge the
high-side MOSFET gate (Q1). During this transition,
charge is transferred from CBOOT to Q1 gate. As Q1
turns on, SW rises to VIN, forcing the BOOT pin to VIN
+VC(BOOT), which provides sufficient VGS enhancement
for Q1. To complete the switching cycle, Q1 is turned off
by pulling HDRV to SW. CBOOT is recharged to VCC
when SW falls to PGND.
HDRV output is in phase with the PWM input. When the
driver is disabled, the high-side gate is held LOW.
Adaptive Gate Drive Circuit
The FAN5109B ensures minimum MOSFET dead-time
while eliminating potential shoot-through (cross-
conduction) currents. It senses the state of the
MOSFETs and adjusts the gate drive, adaptively, to
ensure they do not conduct simultaneously. Refer to the
gate drive rise and fall time waveforms shown in Figure
7 and Figure 8 for the relevant timing information.
To prevent overlap during the LOW-to-HIGH switching
transition (Q2 OFF to Q1 ON), the adaptive circuitry
monitors the voltage at the LDRV pin. When the PWM
signal goes HIGH, Q2 begins to turn OFF after a
propagation delay, as defined by tpdl(LDRV) parameter.
Once the LDRV pin is discharged below ~1.2V, Q1
begins to turn ON after the adaptive delay tpdh(HDRV).
To preclude overlap during the HIGH-to-LOW transition
(Q1 OFF to Q2 ON), the adaptive circuitry monitors the
voltage at the SW pin. When the PWM signal goes
LOW, Q1 begins to turn OFF after a propagation delay
(tpdl(HDRV)). Once the SW pin falls below VCC/3, Q2
begins to turn ON after the adaptive delay tpdh(LDRV).
Additionally, VGS of Q1 is monitored. When VGS(Q1) is
discharged below ~1.2V, a secondary adaptive delay is
initiated, which results in Q2 being driven ON after
tpdh(LDF), regardless of the SW state. This function is
implemented to ensure CBOOT is recharged after each
switching cycle, particularly for cases where the power
converter is sinking current and the SW voltage does
not fall below the VCC/3 adaptive threshold. The
secondary delay tpdh(LDF) is longer than tpdh(LDRV).
OD (aka #OD)
When the OD signal is HIGH, the driver is enabled and
the PWM signal controls the HDRV and LDRV outputs.
When the OD signal is LOW, the driver is disabled and
the PWM signal is ignored. When the OD signal is
LOW, both the HDRV and LDRV outputs are forced
LOW to turn off both the upper and lower output FETs.
© 2006 Fairchild Semiconductor Corporation
FAN5109B Rev. 1.0.0
10 of 14
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