FAN3121_13 Datasheet, PDF (20/21 Pages) Fairchild Semiconductor – Single 9-A High-Speed, Low-Side Gate Driver

Physical Dimensions (Continued)
5.00
4.80
3.81
8
A
5
B
6.20
5.80
4.00
3.80
1.75
0.65
5.60
PIN ONE
1
INDICATOR
(0.33)
0.25
0.10
1.75 MAX
4
1.27
0.25
CBA
1.27
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
C
0.19
R0.10
R0.10
8°
0°
0.90
0.40
0.51
0.33
0.10
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08Arev14
F) FAIRCHILD SEMICONDUCTOR.
Figure 56. 8-Lead Small Outline Integrated Circuit (SOIC)
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without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 • Rev. 1.0.2
20
www.fairchildsemi.com