FAN3121_13 Datasheet, PDF (2/21 Pages) Fairchild Semiconductor – Single 9-A High-Speed, Low-Side Gate Driver

Ordering Information
Part Number
Logic
Input
Threshold
Package
Packing
Method
Quantity
per Reel
FAN3121CMPX
FAN3121CMX
FAN3121CMX_F085⁽¹⁾
FAN3121TMPX
FAN3121TMX
FAN3121TMX_F085 ⁽¹⁾
FAN3122CMPX
FAN3122CMX
FAN3122CMX_F085⁽¹⁾
FAN3122TMPX
FAN3122TMX
FAN3122TMX_F085⁽¹⁾
Inverting
Channels +
Enable
Non-Inverting
Channels +
Enable
CMOS
TTL
CMOS
TTL
3x3 mm MLP-8
SOIC-8
SOIC-8
3x3 mm MLP-8
SOIC-8
SOIC-8
3x3 mm MLP-8
SOIC-8
SOIC-8
3x3 mm MLP-8
SOIC-8
SOIC-8
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
3,000
2,500
2,500
3,000
2,500
2,500
3,000
2,500
2,500
3,000
2,500
2,500
All standard Fairchild Semiconductor products are RoHS compliant and many are also “Green” or going green. Green means the
products are RoHS compliant AND they have limits on additional substances of Chlorine, Bromine and Antimony. For additional
information on Fairchild’s “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Note:
1. Qualified to AEC-Q100.
Package Outlines
Figure 3. 3x3 mm MLP-8 (Top View)
Figure 4. SOIC-8 (Top View)
Thermal Characteristics⁽²⁾
Package
8-Lead 3x3 mm Molded Leadless Package (MLP)
8-Pin Small Outline Integrated Circuit (SOIC)
_JL(3)
1.2
38
_JT(4)
64
29
_JA(5)
42
87
_JB(6)
2.8
41
_JT(7)
0.7
2.3
Units
°C/W
°C/W
Notes:
2. Estimates derived from thermal simulation; actual values depend on the application.
3. Theta_JL (_JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
4. Theta_JT (_JT): Thermal resistance between the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
5. Theta_JA (Θ_JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards
JESD51-2, JESD51-5, and JESD51-7, as appropriate.
6. Psi_JB (_JB): Thermal characterization parameter providing correlation between semiconductor junction
temperature and an application circuit board reference point for the thermal environment defined in Note 5. For
the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and
protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB
copper adjacent to pin 6.
7. Psi_JT (_JT): Thermal characterization parameter providing correlation between the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 5.
© 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 • Rev. 1.0.2
2
www.fairchildsemi.com