GTLP17T616 Datasheet, PDF (2/10 Pages) Fairchild Semiconductor – 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock

Pin Descriptions
Connection Diagram
Pin Names Description
OEAB
A-to-B Output Enable
(Active LOW) (LVTTL levels)
OEBA
B-to-A Output Enable
(Active LOW) (LVTTL levels)
CEAB
A-to-B Clock/LE Enable
(Active LOW) (LVTTL levels)
CEBA
B-to-A Clock/LE Enable
(Active LOW) (LVTTL levels)
LEAB
A-to-B Latch Enable
(Transparent HIGH) (LVTTL levels)
LEBA
B-to-A Latch Enable
(Transparent HIGH) (LVTTL levels)
V_REF
GTLP Input Threshold
Reference Voltage
CLKAB
A-to-B Clock (LVTTL levels)
CLKBA
B-to-A Clock (LVTTL levels)
A1–A17
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B1–B17
B-to-A Data Inputs or
A-to-B Open Drain Outputs (GTLP Levels)
CLKIN
B-to-A Buffered Clock Output
(LVTTL levels)
CLKOUT GTLP Buffered Clock Input/Output of CLKAB
(GTLP Levels)
Truth Table (Note 1)
CEAB
OEAB
Inputs
LEAB
Output
B
CLKAB
A
Mode
X
H
X
X
X
Z
Latched
L
L
L
H or L
X B₀ (Note 2) storage
L
L
L
H or L
X B₀ (Note 3) of A data
X
L
H
X
L
L
Transparent
X
L
H
X
H
H
L
L
L
↑
L
L
Clocked
L
L
L
↑
H
H
storage
of A data
H
L
L
X
X B₀ (Note 3) Clock inhibit
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
Note 2: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 3: Output level before the indicated steady-state input conditions were established.
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