GTLP17T616 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock

January 2000
Revised February 2000
GTLP17T616
17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
General Description
The GTLP17T616 is a 17-bit registered bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
flow and provides a buffered GTLP (CLKOUT) clock output
from the LVTTL CLKAB. The device provides a high speed
interface between cards operating at LVTTL logic levels
and a backplane operating at GTLP logic levels. High
speed backplane operation is a direct result of GTLP’s
reduced output swing (<1V), reduced input threshold levels
and output edge rate control. The edge rate control mini-
mizes bus settling time. GTLP is a Fairchild Semiconductor
derivative of the Gunning Transistor logic (GTL) JEDEC
standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down high impedance for live insertion
s External V_REF pin for receiver threshold adjustability
s BiCMOS technology for low power dissipation
s Bushold data inputs on A Port eliminates the need for
external pull-up resistors for unused inputs
s LVTTL compatible Driver and Control inputs
s Flow-through architecture optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A Port source/sink −24 mA/+24 mA
s B Port sink capability +50 mA
s D-type flip-flop, latch and transparent data paths
s GTLP Buffered CLKAB signal available (CLKOUT)
s −40°C to +85°C Temperature operation
Ordering Code:
Order Number Package Number
Package Description
GTLP17T616MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
GTLP17T616MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS500327
www.fairchildsemi.com