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FXL2TD245 Datasheet, PDF (2/12 Pages) Fairchild Semiconductor – Low Voltage Dual Supply 2-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels 3-STATE Outputs and Independent
Functional Diagram
VCCA
OE
A0
T/R0
A1
T/R1
VCCB
B0
B1
Connection Diagram
B0 B1 OE T/R1
9
8
7
6
VCCB 10
5 GND
1
2
3
4
VCCA A0 A1 T/R0
(Top View)
Pin Assignment
Pin Number
1
2
3
4
5
6
7
8
9
10
Terminal Name
VCCA
A0
A1
T/R0
GND
T/R1
OE
B1
B0
VCCB
Pin Descriptions
Pin Names
Description
OE
Output Enable Input
T/Rn
An
Bn
VCCA
VCCB
Transmit/Receive Inputs
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Side A Power Supply
Side B Power Supply
Truth Table
Inputs
OE T/R0 T/R1
Outputs
L
L
X B0 Data to A0 Output
L H X A0 Data to B0 Output
L
X
L B1 Data to A1 Output
L
X
H A1 Data to B1 Output
H X X 3-STATE
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Power-Up/Power-Down Sequencing
FXL translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0 volts, outputs are in
a HIGH-Impedance state. The control inputs (T/Rn and
OE) are designed to track the VCCA supply. A pull-up
resistor tying OE to VCCA should be used to ensure that
bus contention, excessive currents, or oscillations do not
occur during power-up/power-down. The size of the pull-
up resistor is based upon the current-sinking capability
of the OE driver.
The recommended power-up sequence is the following:
1. Apply power to either VCC.
2. Apply power to the T/Rn inputs (Logic HIGH for A-to-B
operation; Logic LOW for B-to-A operation) and to the
respective data inputs (A Port or B Port). This may
occur at the same time as Step 1.
3. Apply power to other VCC.
4. Drive the OE input LOW to enable the device.
The recommended power-down sequence is the follow-
ing:
1. Drive OE input HIGH to disable the device.
2. Remove power from either VCC.
3. Remove power from other VCC.
©2005 Fairchild Semiconductor Corporation
FXL2TD245 Rev. 1.0.4
2
www.fairchildsemi.com