FAN5093 Datasheet, PDF (2/17 Pages) Fairchild Semiconductor – Two Phase Interleaved Synchronous Buck Converter for VRM 9.x Applications

FAN5093
Pin Assignments
VID0
VID1
VID2
VID3
VID4
BYPASS
AGND
LDRVB
PGNDB
SWB
HDRVB
BOOTB
1
24
2
23
3
22
4
21
5
20
6
FAN5093
19
7
18
8
17
9
16
10
15
11
14
12
13
VFB
RT
ENABLE/SS
DROOP/E*
ILIM
PWRGD
VCC
LDRVA
PGNDA
SWA
HDRVA
BOOTA
PRODUCT SPECIFICATION
Pin Definitions
Pin Number Pin Name
1-5
VID0-4
6
BYPASS
7
AGND
8
LDRVB
9
PGNDB
10
SWB
11
HDRVB
12
BOOTB
13
BOOTA
14
HDRVA
15
SWA
16
PGNDA
17
LDRVA
18
VCC
19
PWRGD
Pin Function Description
Voltage Identification Code Inputs. Open collector/TTL compatible inputs will
program the output voltage over the ranges specified in Table 1. Internally Pulled-
Up.
5V Rail. Bypass this pin with a 0.1µF ceramic capacitor to AGND.
Analog Ground. Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
Low Side FET Driver for B. Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5".
Power Ground B. Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
High side driver source and low side driver drain switching node B. Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
High Side FET Driver B. Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5".
Bootstrap B. Input supply for high-side MOSFET.
Bootstrap A. Input supply for high-side MOSFET.
High Side FET Driver A. Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5".
High side driver source and low side driver drain switching node A. Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
Power Ground A. Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
Low Side FET Driver for A. Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5".
VCC. Internal IC supply. Connect to system 12V supply, and decouple with a 10Ω
resistor and 1µF ceramic capacitor.
Power Good Flag. An open collector output that will be logic LOW if the output
voltage is less than 350mV less than the nominal output voltage setpoint. Power
Good is prevented from going low until the output voltage is out of spec for
500µsec.
2
REV. 1.1.0 3/27/03