FAN3268 Datasheet, PDF (2/16 Pages) Fairchild Semiconductor – 2A Low-Voltage PMOS-NMOS Bridge Driver

Ordering Information
Part Number
FAN3268TMX
Logic
Non-Inverting Channel and
Inverting Channel + Dual Enables
Input Threshold
TTL
Eco Status
RoHS
Packing Method
2,500 Units on
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Package Outline
Figure 2. Pin Configuration (Top View)
Thermal Characteristics⁽¹⁾
Package
8-Pin Small Outline Integrated Circuit (SOIC)
Θ_JL(2)
40
Θ_JT(3)
31
Θ_JA(4)
89
Ψ_JB(5)
43
Ψ_JT(6)
3
Units
°C/W
Notes:
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
3. Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
4. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and
JESD51-7, as appropriate.
5. Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board
reference is defined as the PCB copper adjacent to pin 6.
6. Psi_JT (ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 4.
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.0
2
www.fairchildsemi.com