74F569 Datasheet, PDF (2/9 Pages) NXP Semiconductors – 4-bit bidirectional binary synchronous counter 3-State

Unit Loading/Fan Out
Pin Names
P₀–P₃
CEP
CET
CP
PE
U/D
OE
MR
SR
O₀–O₃
TC
CC
Description
Parallel Data Inputs
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Enable Input (Active LOW)
Up/Down Count Control Input
Output Enable Input (Active LOW)
Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
3-STATE Parallel Data Outputs
Terminal Count Output (Active LOW)
Clocked Carry Output (Active LOW)
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40(33.3)
50/33.3
50/33.3
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
−1 mA/20 mA
−1 mA/20 mA
Functional Description
The 74F569 counts in the modulo-16 binary sequence.
From state 15 it will increment to state 0 in the Up mode; in
the Down mode it will decrement from 0 to 15. The clock
inputs of all flip-flops are driven in parallel through a clock
buffer. All state changes (except due to Master Reset)
occurs synchronously with the LOW-to-HIGH transition of
the Clock Pulse (CP) input signal.
The circuits have five fundamental modes of operation, in
order of precedence: asynchronous reset, synchronous
reset, parallel load, count and hold. Five control inputs—
Master Reset (MR), Synchronous Reset (SR), Parallel
Enable (PE), Count Enable Parallel (CEP) and Count
Enable Trickle CET)—plus the Up/Down (U/D) input, deter-
mine the mode of operation, as shown in the Mode Select
Table. A LOW signal on MR overrides all other inputs and
asynchronously forces the flip-flop Q outputs LOW. A LOW
signal on SR overrides counting and parallel loading and
allows the Q outputs to go LOW on the next rising edge of
CP. A LOW signal on PE overrides counting and allows
information on the Parallel Data (P_n) inputs to be loaded
into the flip-flops on the next rising edge of CP. With MR,
SR and PE HIGH, CEP and CET permit counting when
both are LOW. Conversely, a HIGH signal on either CEP or
CET inhibits counting.
The 74F569 uses edge-triggered flip-flops and changing
the SR, PE, CEP, CET or U/D inputs when the CP is in
either state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising
edge of CP, are observed.
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally
HIGH and goes LOW providing CET is LOW, when the
counter reaches zero in the Down mode, or reaches maxi-
mum
(15) in the Up mode. TC will then remain LOW until a state
change occurs, whether by counting or presetting, or until
U/D or CET is changed. To implement synchronous multi-
stage counters, the connections between the TC output
and the CEP and CET inputs can provide either slow or
fast carry propagation.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in Figure 2
are recommended. In this scheme the ripple delay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min in
the Up mode, or min to max in the Down mode, to start its
final cycle. Since this final cycle takes 16 clocks to com-
plete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
counters. For such applications, the Clocked Carry (CC)
output is provided. The CC output is normally HIGH. When
CEP, CET, and TC are LOW, the CC output will go LOW
when the clock next goes LOW and will stay LOW until the
clock goes HIGH again, as shown in the CC Truth Table.
When the Output Enable (OE) is LOW, the parallel data
outputs O₀–O₃ are active and follow the flip-flop Q outputs.
A HIGH signal on OE forces O₀–O₃ to the High Z state but
does not prevent counting, loading or resetting.
Logic Equations
Count Enable = CEP • CET • PE
Up: TC = Q₀ • Q₁ • Q₂ • Q₃ • (Up) • CET
Down: TC = Q₀ • Q₁ • Q₂ • Q₃ • (Down) • CET
www.fairchildsemi.com
2