FAN3223_12 Datasheet, PDF (19/24 Pages) Fairchild Semiconductor – Dual 4A High-Speed, Low-Side Gate Drivers

Truth Table of Logic Operation
The FAN3225 truth table indicates the operational states
using the dual-input configuration. In a non-inverting
driver configuration, the IN- pin should be a logic LOW
signal. If the IN- pin is connected to logic HIGH, a disable
function is realized, and the driver output remains LOW
regardless of the state of the IN+ pin.
IN+
IN-
OUT
0
0
0
0
1
0
1
0
1
1
1
0
Operational Waveforms
At power-up, the driver output remains LOW until the
V_DD voltage reaches the turn-on threshold. The
magnitude of the OUT pulses rises with V_DD until
steady-state V_DD is reached. The non-inverting
operation illustrated in Figure 51 shows that the output
remains LOW until the UVLO threshold is reached, then
the output is in-phase with the input.
In the non-inverting driver configuration in Figure 49, the
IN- pin is tied to ground and the input signal (PWM) is
applied to IN+ pin. The IN- pin can be connected to logic
HIGH to disable the driver and the output remains LOW,
regardless of the state of the IN+ pin.
Figure 49. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver application in Figure 50, the IN+
pin is tied HIGH. Pulling the IN+ pin to GND forces the
output LOW, regardless of the state of the IN- pin.
Figure 51. Non-Inverting Start-Up Waveforms
For the inverting configuration of Figure 50, start-up
waveforms are shown in Figure 52. With IN+ tied to
VDD and the input signal applied to IN–, the OUT
pulses are inverted with respect to the input. At power-
up, the inverted output remains LOW until the V_DD
voltage reaches the turn-on threshold, then it follows the
input with inverted phase.
Figure 50. Dual-Input Driver Enabled,
Inverting Configuration
© 2012 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225_F085 • Rev. 1.0.0
Figure 52. Inverting Start-Up Waveforms
www.fairchildsemi.com
19