TMC2250A Datasheet, PDF (18/23 Pages) Fairchild Semiconductor – Matrix Multiplier 12 x 10 bit, 50 MHz

PRODUCT SPECIFICATION
TMC2250A
Switching Characteristics
Parameter
t_DO Output Delay Time
t_HO Output Hold Time
Conditions
C_LOAD = 25 pF
C_LOAD = 25 pF
Min
Typ
Max Units
15
ns
3
ns
Application Notes
Performing Large-Kernel Pixel Interpolation
The Cascade Input and Output Ports of the TMC2250A allow the user to stack multiple devices to perform larger interpolation
kernels with no decrease in pixel throughput. Figure 12 illustrates a basic application utilizing Mode 11 to realize a 4 x 4-pixel
kernel, also called Cubic Convolution. This example utilizes the TMC2011A Variable-Length Shift Register to compensate for
the internal latency of each TMC2250A. Alternatively, some applications may utilize RAM, FIFO's, or other methods to store
multiple-line pixel data. In these cases the user may compensate for latency by simply offsetting the access sequencing of the
storage devices.
A ₁₂
B
12
A
4 X 2 TMC2250A
B _CASOUT
16
C
12
D
12
3 X TMC2111A
A ^CASIN
4 X 2 TMC2250A
B _CASOUT
16
OUTPUT
Figure 12. Figure 12. Performing Cubic Convolution with Two TMC2250A's
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REV. 1.0.2 10/25/00