TMC2250A Datasheet, PDF (14/23 Pages) Fairchild Semiconductor – Matrix Multiplier 12 x 10 bit, 50 MHz

PRODUCT SPECIFICATION
TMC2250A
4 x 2-Pixel Cascadeable Convolver
(Mode 11)
Similar to Mode 10, the 4 x 2 -Pixel convolver allows the use
to perform full-speed cubic convolution with only two
TMC2250A devices and the TMC2111A Pipeline Delay
Register to synchronize the cascade ports (see the Applica-
tions Discussion section).
Pixel data are side-loaded into ports A and B, multiplied by
the onboard coefficients, summed with the cascade input,
and half-LSB rounded to 16 bits. The four-cycle impulse
response emerges at the cascade output port 5 to 8 clock
cycles later. A new output word is available on every clock
cycle. Note that Multiplier KC2 is not used in this mode and
that its stored coefficient is ignored.
As shown below, the column of input pixel data is automati-
cally shifted one location to the right through the two rows of
multiplier input registers on every clock in anticipation of
two new input data words, effectively sliding the convolu-
tional window over one column in an image plane.
CASOUT(8)=
A(4)KA3(4)+A(3)KA2(3)+A(2)KA1(2)
+A(1)KB3(4)+B(4)KB3(4)+B(3)KB2(3)
+B(2)KB1(2)+B(1)KC1(2)+CASIN(5)
1
2
3
4
5
6
7
8
9
10
11
CLK
CWE
01
10
11
00
KA, KB, KC
K_1
K_2
K_3
DATA IN A, B
1.0
MODE
11
CASIN
CASOUT
Q8
KA3 + KB3
KA1 + KB1
Q8
KA2 + KB2
KC1 + KC3
Figure 7. 4 x 2-Pixel Convolver Impulse Response (Mode 11)
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REV. 1.0.2 10/25/00