FAN5092MTC Datasheet, PDF (14/20 Pages) Fairchild Semiconductor – High Current System Voltage Buck Converter

FAN5092
PRODUCT SPECIFICATION
tant to connect the PGND and SW pins for each phase as a
Kelvin trace pair directly to the source and drain, respec-
tively, of the appropriate low-side MOSFET. Care is required
in the layout of these grounds; see the layout guidelines in
this datasheet.
Current Sharing
The two independent current sensors of the FAN5092 operate
with their independent current control loops to guarantee that
the two phases each deliver half of the total output current.
The only mismatch between the two phases occurs if there is
a mismatch between the RDS,on of the low-side MOSFETs.
In normal usage, two FAN5092s will be operated in parallel.
By connecting the ISHR pins together, the two error amps of
the two ICs will be forced to operate at exactly the same duty
cycle, thus ensuring very close matching of the currents of
all four phases.
Short Circuit Current Characteristics
The FAN5092 short circuit current characteristic includes a
function that protects the DC-DC converter from damage in
the event of a short circuit. The short circuit limit is given by
the formula
I_SC = ₁----₀-----_•----^6R---^V--_D---_S----_,--_o---_n-
per phase.
Precision Current Sensing
The tolerances associated with the use of MOSFET current
sensing can be circumvented by the use of a current sense
resistor.
E*-mode
Further enhancement in efficiency can be obtained by putting
the FAN5092 into E*-mode. When the Droop pin is pulled to
the 5V BYPASS voltage, the “A” phase of the FAN5092 is
completely turned off, reducing in half the amount of gate
charge power being consumed. E*-mode can be imple-
mented with the circuit shown in Figure 3:
+12V
10KΩ
HI = E*-
mode on
10KΩ
10KΩ
2N2222
2N2907
FAN5092
pin25
R_DROOP
Figure 3. Implementing E*-mode Control
Note that the charge pump for the HIDRVs should be based
on the “B” phase of the FAN5092, since the “A” phase is off
in E*-mode.
Internal Voltage Reference
The reference included in the FAN5092 is a precision band-
gap voltage reference. Its internal resistors are precisely
trimmed to provide a near zero temperature coefficient (TC).
Based on the reference is the output from an integrated 5-bit
DAC. The DAC monitors the 5 voltage identification pins,
VID0-4, and scales the reference voltage from 1.100V to
1.850V in 25mV steps.
BYPASS Reference
The internal logic of the FAN5092 runs on 5V. To permit the
IC to run with 12V only, it produces 5V internally with a
linear regulator, whose output is present on the BYPASS pin.
This pin should be bypassed with a 1µF capacitor for noise
suppression. The BYPASS pin should not have any external
load attached to it.
Dynamic Voltage Adjustment
The FAN5092 has interal pullups on its VID lines. External
pullups should not be used. The FAN5092 can have its output
voltage dynamically adjusted to accommodate low power
modes. The designer must ensure that the transitions on the
VID lines all occur simultaneously (within less than 500nsec)
to avoid false codes generating undesired output voltages.
The Power Good flag tracks the VID codes, but has a
500µsec delay transitioning from high to low; this is long
enough to ensure that there will not be any glitches during
dynamic voltage adjustment.
Power Good (PWRGD)
The FAN5092 Power Good function is designed in accor-
dance with the Pentium IV DC-DC converter specifications
and provides a continuous voltage monitor on the VFB pin.
The circuit compares the VFB signal to the VREF voltage
and outputs an active-low interrupt signal to the CPU should
the power supply voltage deviate more than +15%/-11% of
its nominal setpoint. The output is guaranteed open-collector
high when the power supply voltage is within +8%/-18% of
its nominal setpoint. The Power Good flag provides no
control functions to the FAN5092.
Output Enable/Soft Start (ENABLE/SS)
The FAN5092 will accept an open collector/TTL signal for
controlling the output voltage. The low state disables the
output voltage. When disabled, the PWRGD output is in the
low state.
Even if an enable is not required in the circuit, this pin
should have attached a capacitor (typically 100nF) to soft-
start the switching. A softstart capacitor may be approxi-
mately chosen by the formula:
C = ^t-₁---^•--+--¹---_V0----^µ_o---_u-^A--_t
However, C must be ≥ 100nF.
14
REV. 1.0.7 6/20/02