FAN5092MTC Datasheet, PDF (13/20 Pages) Fairchild Semiconductor – High Current System Voltage Buck Converter

PRODUCT SPECIFICATION
FAN5092
Application Information
Operation
The FAN5092 Controller
The FAN5092 is a programmable synchronous multi-phase
DC-DC controller IC. It can be run as a single controller, and
a second FAN5092 can then be paralleled modularly for
higher currents. When designed around the appropriate
external components, the FAN5092 can be configured to
deliver more than 120A of output current. The FAN5092
functions as a fixed frequency PWM step down regulator,
with a high efficiency mode (E*) at light load.
Main Control Loop
Refer to the FAN5092 Block Diagram on page 7. The
FAN5092 consists of two interleaved synchronous buck
converters, implemented with summing-mode control. Each
phase has its own current feedback, and there is a common
voltage feedback.
The two buck converters controlled by the FAN5092 are
interleaved, that is, they run 180° out of phase with each
other. This minimizes the RMS input ripple current, mini-
mizing the number of input capacitors required. It also
doubles the effective switching frequency, improving
transient response.
The FAN5092 implements “summing mode control”, which
is different from both classical voltage-mode and current-
mode control. It provides superior performance to either by
allowing a large converter bandwidth over a wide range of
output loads and external components.
The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
feeding into a comparator which provides the input to the
digital control block. The signal conditioning section accepts
inputs from a current sensor and a voltage sensor, with the
voltage sensor being common to both slices, and the current
sensor separate for each. The voltage sensor amplifies the
difference between the VFB signal and the reference voltage
from the DAC and presents the output to each of the two
comparators. The current control path for each slice takes the
difference between its PGND and SW pins when the low-
side MOSFET is on, reproducing the voltage across the
MOSFET and thus the input current; it presents the resulting
signal to the same input of its summing amplifier, adding its
signal to the voltage amplifier’s with a certain gain. These
two signals are thus summed together. This sum is then pre-
sented to a comparator looking at the oscillator ramp, which
provides the main PWM control signal to the digital control
block. The oscillator ramps are 180° out of phase with each
other, so that the two slices are on alternately.
The digital control block takes the analog comparator input
to provide the appropriate pulses to the HDRV and LDRV
output pins for each slice. These outputs control the external
power MOSFETs.
Remote Voltage Sense
The FAN5092 has true remote voltage sense capability, elim-
inating errors due to trace resistance. To utilize remote sense,
the VFB and AGND pins should be connected as a Kelvin
trace pair to the point of regulation, such as the processor
pins. The converter will maintain the voltage in regulation at
that point. Care is required in layout of these grounds; see
the layout guidelines in this datasheet.
High Current Output Drivers
The FAN5092 contains four high current output drivers that
utilize MOSFETs in a push-pull configuration. The drivers
for the high-side MOSFETs use the BOOT pin for input
power and the SW pin for return. The drivers for the low-side
MOSFETs use the VCC pin for input power and the PGND
pin for return. Typically, the BOOT pin will use a charge
pump as shown in Figure 1. Note that the BOOT and VCC
pins are separated from the chip’s internal power and ground,
BYPASS and AGND, for switching noise immunity.
Adaptive Delay Gate Drive
The FAN5092 embodies an advanced design that ensures
minimum MOSFET transition times while eliminating
shoot-through current. It senses the state of the MOSFETs
and adjusts the gate drive adaptively to ensure that they are
never on simultaneously. When the high-side MOSFET turns
off, the voltage on its source begins to fall. When the voltage
there reaches approximately 2.5V, the low-side MOSFETs
gate drive is applied with approximately 50nsec delay. When
the low-side MOSFET turns off, the voltage at the LDRV pin
is sensed. When it drops below approximately 2V, the high-
side MOSFET’s gate drive is applied.
Maximum Duty Cycle
In order to ensure that the current-sensing and charge-
pumping work, the FAN5092 guarantees that the low-side
MOSFET will be on a certain portion of each period. For low
frequencies, this occurs as a maximum duty cycle of approxi-
mately 90%. Thus at 250KHz, with a period of 4µsec, the
low-side will be on at least 4µsec • 10% = 400nsec. At higher
frequencies, this time might fall so low as to be ineffective.
The FAN5092 guarantees a minimum low-side on-time of
approximately 330nsec, regardless of what duty cycle this
corresponds to.
Current Sensing
The FAN5092 has two independent current sensors, one for
each phase. Current sensing is accomplished by measuring
the source-to-drain voltage of the low-side MOSFET during
its on-time. Each phase has its own power ground pin, to
permit the phases to be placed in different locations without
affecting measurement accuracy. For best results, it is impor-
REV. 1.0.7 6/20/02
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