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FOD8160 Datasheet, PDF (13/15 Pages) Fairchild Semiconductor – High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Package Dimensions
3.95
1.27
A
6
0.20 C A-B
2X
D
4
4.60
9.20
11.80
11.60
6
1.38
1.27
0.60
4
11.38
0.10 C D
1
3
2X
PIN ONE
INDICATOR
B
2.54
5X
0.51
0.31
1
3
0.33 C
0.25 C A-B D
5 TIPS
2.54
LAND PATTERN
RECOMMENDATION
2.65
A
2.45
0.10 C
SEATING
2.90
PLANE
2.60
0.30
0.10 C
0.10
C 5X
GAUGE
PLANE
0.25 C
1.35
1.15
8°
0°
(R1.29)
0.74
0.44
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE DOES NOT
CONFORM TO ANY STANDARD.
B) ALL DIMENSIONS ARE IN
(R0.54) MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF
BURRS, MOLD FLASH AND TIE BAR
PROTRUSIONS
0.25
0.19
D) DRAWING CONFORMS TO ASME
Y14.5M-1994
E) DRAWING FILE NAME:
MKT-M05AREV2
SEATING
PLANE
SCALE: 3.2:1
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
13
www.fairchildsemi.com