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| FOD8160 Datasheet, PDF (10/15 Pages) Fairchild Semiconductor – High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin | |||
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Test Circuit
Pulse Gen.
IF
5 MHz
tf = tr = 5 ns
DC = 50%
Input
Monitoring
Mode
RM
0.1 μF
Bypass
350 Ω
VO Monitoring
CLNode
Input
(IF = 6 mA)
50%
Output
tf
tPHL
tPLH
tr
90%
1.5 V
10%
VOL
Figure 13. Test Circuit for Propagation Delay, Rise Time, and Fall Time
IF
SW
RM
0.1 μF
Bypass
VCC
350 Ω
VO Monitoring
CL Node
VCM
Pulse Gen
VCM 90%
1 kV
10%
tr
VO (IF = 0 mA)
0V
tf
VOH
2V
VO (IF = 6 mA)
0.8 V
VOL
Figure 14. Test Circuit for Instantaneous Common-Mode Rejection Voltage
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
10
www.fairchildsemi.com
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