FAN5182 Datasheet, PDF (13/18 Pages) Fairchild Semiconductor – Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller

Selecting a Standard Inductor
The following power inductor manufacturers can provide design
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• Coilcraft
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• Coiltronics
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• Sumida Electric Company
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• Vishay Intertechnology
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Output Current Sense
The output current can be measured by summing the voltage
across each inductor and passing the signal through a low-pass
filter. The CS amplifier is configured with resistors R_PH(X) (for
summing the voltage), and R_CS and C_CS (for the low-pass filter).
The output current I_O is set by the following equations:
I_O
=
R_{----P----H---(--x---) ×} V_{----D----R---P--}
R_CS
R_L
(6)
C_CS ≥ _R----_L-----_×-^L---_R----_C----_S
(7)
where:
R_L is the DCR of the output inductors.
V_DRP is the voltage drop from CSCOMP to CSREF.
When load current reaches its limit, V_DRP is at its maximum
(V_DRPMAX). V_DRPMAX can be in the range of 100mV to 200mV.
In this example, it is 110mV.
One has the flexibility of choosing either R_CS or R_PH(X). It is rec-
ommended to select R_CS equal to 100kΩ, and then solve for
R_PH(X) by rearranging Equation 6.
R_PH(x)
=
R_L
×
R_CS
×
-------^I--^L---^I--^M---------
V_DRPMAX
R_PH(x)
=
1.4
mΩ
×
100kΩ
×
---¹---¹---⁰---^A------
110mV
=
140kΩ
Next, use Equation 7 to solve for C_CS.
C_CS ≥ ₁----_.-₄---_m-----⁶_Ω---⁰---⁰-_×--ⁿ--₁-^H--₀---₀----_k---_Ω--- ≥ 4.29nF
Choose the closest standard value that is greater than the result
given by Equation 7. This example uses a C_CS value of 5.6nF.
Output Voltage
FAN5182 has an internal FBRTN referred 800mV voltage refer-
ence (V_REF). The output voltage can be set by using a voltage
divider consists of resistors R_B1 and R_B2:
V_OUT
=
(_---R_{----B---1----+-----}R_{----B----2---})
R_B1
×
V_REF
(8)
Rearranging Equation 8 to solve R_B2 and assuming a 1%, 1kΩ
resistor for R_B1 yields
R_B2
=
V_{----O----U----T----}–_----V_{----R----E---F-}
V_REF
×
R_B1
R_B2
=
1_----._-8_---V_{------–-----}0_---._-8_----V_--
0.8V
×
1
kΩ
=
1.25kΩ
The closest standard 1% resistor value for R_B2 is 1.24kΩ.
Power MOSFETs
For this example, one high-side and one low-side N-channel
power MOSFETs per phase have been selected. The main
selection parameters for power MOSFETs are V_GS(TH), Q_G,
C_ISS, C_RSS, and R_DS(ON). The minimum gate drive voltage (the
supply voltage to the FAN5009) dictates whether standard
threshold or logic-level threshold MOSFETs can be used. With
V_GATE ~10V, logic-level threshold MOSFETs (V_GS(TH) < 2.5V)
are recommended.
The maximum output current (I_O) determines the R_DS(ON)
requirement for the low-side (synchronous) MOSFETs. With
good current balance among phases, the current in each low-
side MOSFET is the output current divided by the total number
of low-side MOSFETs (n_SF). Since conduction loss is dominant
in low-side MOSFET, the following expression can represent
total power dissipation in each synchronous MOSFET in terms
of the ripple current per phase (I_R) and the total output current
(I_O):
P_SF = (1 – D) ×


n^--I--_SO^--_F^{--}
2
+
--¹---
12
×


-ⁿ--_n--^×--_S--_F-^I--^R-_
2
× R_DS(SF)
(9)
Knowing the maximum output current and the maximum
allowed power dissipation, one can determine the required
R_DS(ON) for the MOSFET. For example, D-PAK MOSFETs oper-
ating up to ambient temperature of 50°C, a safe limit for P_SF is
around 1W to 1.5W at 120°C junction temperature. Therefore, in
this example, R_DS(SF) (per MOSFET) < 7.5mΩ. This R_DS(SF) is
typically measured at junction temperature of about 120°C In
this example, we select a lower-side MOSFET with 4.8mΩ at
120°C.
Another important consideration for choosing the synchronous
MOSFET is the input capacitance and feedback capacitance.
The ratio of feedback to input capacitance must be small (less
than 10% is recommended) in order to preventing accidentally
turning on the synchronous MOSFETs when the switch node
goes high.
Also, the time to switch the synchronous MOSFETs off should
not exceed the non-overlap dead time of the MOSFET driver
(40ns typical for the FAN5009). The output impedance of the
driver is approximately 2Ω, and the typical MOSFET input gate
resistances are about 1Ω to 2Ω. Therefore, the total gate capac-
itance should be less than 6000pF. In the event there are two
MOSFETs in parallel, the input capacitance for each synchro-
nous MOSFET should be limited to 3000pF.
The high-side (main) MOSFET power dissipation consists of
two elements: conduction and switching losses. The switching
loss is related to the main MOSFET’s turn on and off time, and
the current and voltage being switched. Based on the main
13
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FAN5182 Rev. 1.0.1