FAN5182 Datasheet, PDF (12/18 Pages) Fairchild Semiconductor – Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller

Application Information
Design parameters for a typical high current point-of-load dc/dc
buck converter shown in Figure 5 are as follows:
• Input voltage (V_IN) = 12V
• Output voltage (V_OUT) = 1.8V
• Duty cycle (D) = 0.15
• Output current I_O = 55A
• Maximum output current (I_LIM) = 110A
• Number of phases (n) = 3
• Switching frequency per phase (f_SW) = 250kHz
Setting the Clock Frequency
The FAN5182 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (R_T). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and the input and output capaci-
tors. With n = 3 for three phases, a clock frequency of 750kHz
sets the switching frequency (f_SW) of each phase to 250kHz,
which represents a practical trade-off between the switching
losses and the sizes of the output filter components.
Equation 1 shows that to achieve a 750kHz oscillator frequency,
the correct value for R_T is 255kΩ. Alternatively, the value for R_T
can be calculated using
R_T = _n-----_×-----_f--_S--_W----¹--_×-----₄---_.-₇---_p----_F-- – 27kΩ
(1)
R_T = -₃----_×-----₂---₅---₀---_k----_H-¹---_z----_×-----₄---_.--₇---_p---_F-- – 27kΩ = 256kΩ
where 4.7pF and 27kΩ are internal IC component values. For
good initial accuracy and frequency stability, a 1% resistor is
recommended. The closest standard 1% value for this design is
255kΩ.
Soft-Start and Current Limit Latch-off Delay Time
Because the soft start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set C_DLY for the soft-start ramp. This
ramp is generated with a 20µA internal current source. The
value of R_DLY has a second-order impact on the soft-start time
because it sinks part of the current source to ground. However,
as long as R_DLY is kept greater than 200kΩ, this effect is minor.
The value for C_DLY can be approximated using:
C_DLY
=
^{20µA – -}₂^----_×^V----R-_R^--E--_D^-F--_L^---_Y^-
× ----^t--^S--^S----
V_REF
(2)
where t_SS is the desired soft-start time. Assuming an R_DLY of
390kΩ and a desired soft-start time of 3ms, C_DLY is 71nF. The
closest standard value for C_DLY is 68nF. Once C_DLY is chosen,
R_DLY can be calculated for the current limit latch-off time using:
R_DLY
=
1_----._-9_---6_-----×_----t_{--D----E---L---A---Y-}
C_DLY
(3)
If the result for R_DLY is less than 200kΩ, a smaller soft-start time
should be considered by recalculating the equation for C_DLY, or
a longer latch-off time should be used. R_DLY should never be
less than 200kΩ. In this example, a delay time of 9ms results in
R_DLY = 259kΩ. The closest standard 1% value is 261kΩ.
Inductor Selection
The inductance determines the ripple current in the inductor.
Small inductance leads to high ripple current, which increases
the output ripple voltage and conduction losses in the MOS-
FETs, and vise versa. In any multiphase converters, it's recom-
mended to design the peak-peak inductor ripple current to be
less than 50% of the maximum inductor dc current.
Equation 4 shows the relationship among the inductance, oscil-
lator frequency, and peak-peak ripple current.
I_R = ^V----^O----^U---_f-^T-_S--_W-^×-----_×(--¹--_L---^–----^D-----⁾
(4)
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
L ≥ ^V----^O----^U----^T---_f-^×-_S---_W-^R----^x_×---^×--_V---⁽-_R-¹--_I--_P-^–--_P---⁽_L--ⁿ-_E---^×-----^D-----⁾---⁾
(5)
where R_X is the ESR of output bulk capacitors.
Solving Equation 5 for a 20mV peak-to-peak output ripple volt-
age and 3mΩ R_X yields
L ≥ ¹----^.-⁸---^V------^×----₂-³--₅-^m--₀---_k^Ω---_H----^×-_z---⁽-_×--¹---₂-–--₀---⁽_m--³---_V--^×-----⁰---^.-¹---⁵---⁾---⁾ = 594nH
If the resulting ripple voltage is too low, the inductance can be
reduced until the desired ripple voltage is achieved. In this
example, a 600nH inductor is a good starting point that pro-
duces a calculated ripple current of 6.6A. The inductor should
not saturate at the peak current of 21.6A, and should be able to
handle the total power dissipation created by the copper and
core loss.
Another important factor in the inductor design is the DCR,
which is used for measuring the phase current. A large DCR
can cause excessive power losses, whereas too small DCR can
increases measurement error. For this design, a DCR of 1.4mΩ
was chosen.
Designing an Inductor
Once the inductance and DCR are known, the next step is to
either design an inductor or find a suitable standard inductor if
one exists. Inductor design starts with choosing appropriate
core material. Some candidate materials that have low core loss
at high frequencies are powder cores (e.g. Kool-Mµ® from Mag-
netics, Inc., or from Micrometals) and gapped soft ferrite cores
(e.g. 3F3 or 3F4 from Philips). Powdered iron cores have higher
core loss, and are used for low cost applications.
The best choice for a core geometry is a closed-loop type, such
as a potentiometer core, a PQ/U/E core, or a toroid core.
Some useful references for magnetics design are
• Magnetic Designer Software
• Intusoft (www.intusoft.com)
• Designing Magnetic Components for High-Frequency DC-DC
Converters, by William T. McLyman, Kg Magnetics, Inc.,
ISBN 1883107008
12
www.fairchildsemi.com
FAN5182 Rev. 1.0.1