FAN1577A Datasheet, PDF (13/15 Pages) Fairchild Semiconductor – Dual Synchronous DC/DC Controller

Layout Considerations
Layout is important in high-frequency switching converter
design. If designed improperly, PCB can radiate
excessive noise and contribute to converter instability.
Place the PWM power-stage components first. Mount
all the power components and connections in the top
layer with wide copper areas. The MOSFETs of buck,
inductor, and output capacitor should be as close to
each other as possible to reduce the radiation of EMI
due to the high-frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
capacitor, equal sharing ripple current should be
considered. Place the input capacitor near the drain of
the high-side MOSFET. In multi-layer PCB, use one
layer as power ground and have a separate control
signal ground as the reference for all signals. To avoid
the signal ground being affected by noise and to
achieve the best load regulation, it should be connected
to the ground terminal of output.
Follow the below guidelines for best performance:
ƒ Keep power traces wide and short to minimize
losses and ringing.
ƒ The small-signal wiring traces from the DLx and
DHx pins to the MOSFET gates should be kept
short and wide enough to easily handle the several
amps of drive current.
ƒ The critical, small-signal components include any
bypass capacitors (SMD-type of capacitors applied
at VCC and SSx/ENB pins), feedback components
(resistor divider), and compensation components
(between INx and COMPx pins). Position those
components close to their pins with a local, clear,
GND connection or directly to the ground plane.
ƒ Place the bootstrap capacitor near the BSTx and
CLNx pins.
ƒ The resistor on the RT pin should be near this pin
and the GND return should be short and kept away
from the noisy MOSFET GND (which is shorted
together with IC PGND pin to GND plane).
ƒ Place the compensation components close to the
INx and COMPx pins.
ƒ The feedback resistors for both regulators should
be located as close as possible to the relevant
INx pin with vias tied straight to the ground plane
as required.
ƒ Minimize the length of the connections between the
input capacitors, CIN, and the power switchers
(MOSFETs) by placing them nearby.
ƒ Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible
and make the GND returns short (from the source
of lower MOSFET to GND of VIN capacitor.
ƒ Position the output inductor and output capacitors
between the upper MOSFET, lower MOSFET, and
the load.
ƒ AGND should be on the clearer plane and kept
away from the noisy MOSFET GND.
ƒ PGND should be short, together with MOSFET
GND, then through a via to the GND plane.
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
13
www.fairchildsemi.com