FAN1577A Datasheet, PDF (12/15 Pages) Fairchild Semiconductor – Dual Synchronous DC/DC Controller

Type II Compensation Design (for Output Capacitors with High ESR)
FAN1577A is a voltage-mode controller. The control
loop is a single-voltage feedback path, including an
error amplifier and PWM comparator, as shown in
Figure 30. To achieve fast transient response and
accurate output regulation, an adequate compensator
design is necessary. A stable control loop has a 0dB
gain crossing with -20dB/decade slope and a phase
margin greater than 45°.
2. Compensation Frequency Equations
The compensation network consists of the error
amplifier and the impedance networks ZC and Zf as
Figure 31 shows.
Figure 31. Compensation Loop
Figure 30. Closed Loop
1. Modulator Frequency Equations
The modulator transfer function is the small-signal
transfer function of VOUT/VE/A. This transfer function is
dominated by a DC gain and the output filter (LO and
CO) with a double-pole frequency at fLC and a zero at
fESR. The DC gain of the modulator is the input voltage
(VIN) divided by the peak-to-peak oscillator voltage
ΔVRAMP(=1.6V). The first step is to calculate the complex
conjugate poles contributed by the LC output filter. The
output LC filter introduces a double pole, -40dB /
decade gain slope above its corner resonant frequency
and a total phase lag of 180 degrees. The resonant
frequency of the LC filter expressed as:
f_P(LC) = _{2π ×}
1
L_O × C_O
(5)
The next step of compensation design is to calculate
the ESR zero contributed by the ESR associated with
the output capacitance. Note that this requires that the
output capacitor have enough ESR to satisfy stability
requirements. The ESR zero of the output capacitor is
expressed as:
f_{Z(ESR )}
=
2π
1
× C_O × ESR
(6)
f_P1 = 0
f_Z1
=
2π
1
× R₂
×
C₂
(7)
f_P2
=
2π
× R₂
1
× (C₁
//
C₂ )
Compensation gain uses external impedance networks
ZC and Zf to provide a stable high-bandwidth loop.
High crossover frequency is desirable for fast transient
response, but often jeopardizes system stability. To
cancel one of the LC filter poles, place the zero before
the LC filter resonant frequency. Place the zero at 75%
of the LC filter resonant frequency. Crossover frequency
should be higher than the ESR zero, but less than 1/5
of the switching frequency. The second pole should be
placed at half the switching frequency.
© 2010 Fairchild Semiconductor Corporation
FAN1577A • Rev. 1.0.0
12
www.fairchildsemi.com