FAN5056MV85 Datasheet, PDF (12/15 Pages) Fairchild Semiconductor – High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms

FAN5056MV85
PRODUCT SPECIFICATION
Adjusting the Linear Regulators’ Output
Voltages
Any or all of the linear regulators’ outputs may be adjusted
high to compensate for voltage drop along traces, as shown
in Figure 5.
VGATE
R
VFB
10KΩ
VOUT
Figure 5. Adjusting the Output Voltage of the
Linear Regulator
The resistor value should be chosen as
R = 2KΩ*
V_out
Vnom
For example, to get the V_ADJ voltage to be 1.50V instead of
1.20V, use R = 2KΩ * [(1.50/1.20) – 1] = 500Ω.
Using the FAN5056 for Vnorthbridge = 1.8V
Similarly, the FAN5056 can also be used to generate Vnorth-
bridge = 1.8V by utilizing the AGP regulator as shown in
Figure 5: tie the TYPEDET pin to ground, and use R = 399Ω.
Coppermine/Tualatin VTT
The adjustable regulator may be used for powering VTT
in systems in which either a Coppermine or a Tualatin
processor may be used, as shown in Figure 6.
VGATE
VTT
100Ω
VFB
10KΩ
487Ω
3.16KΩ
PCB Layout Guidelines
• Placement of the MOSFETs relative to the FAN5056 is
critical. Place the MOSFETs such that the trace length of
the HIDRV and LODRV pins of the FAN5056 to the FET
gates is minimized. A long lead length on these pins will
cause high amounts of ringing due to the inductance of the
trace and the gate capacitance of the FET. This noise
radiates throughout the board, and, because it is switching
at such a high voltage and frequency, it is very difficult to
suppress.
• In general, all of the noisy switching lines should be kept
away from the quiet analog section of the FAN5056. That
is, traces that connect to pins 1, 2, 23, and 24 (HIDRV,
SW, LODRV and V_CCP) should be kept far away from the
traces that connect to pins 3, 20 and 21.
• Place the 0.1µF decoupling capacitors as close to the
FAN5056 pins as possible. Extra lead length on these
reduces their ability to suppress noise.
• Each V_CC and GND pin should have its own via to the
appropriate plane. This helps provide isolation between
pins.
• Place the MOSFETs, inductor, and Schottky as close
together as possible for the same reasons as in the first
bullet above. Place the input bulk capacitors as close to
the drains of the high side MOSFETs as possible. In
addition, placement of a 0.1µF decoupling cap right on
the drain of each high side MOSFET helps to suppress
some of the high frequency switching noise on the input
of the DC-DC converter.
• Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter’s performance under
severe load transient conditions, causing higher voltage
deviation. For more detailed information regarding
capacitor placement, refer to Application Bulletin AB-5.
• A PC Board Layout Checklist is available from Fairchild
Applications. Ask for Application Bulletin AB-11.
Additional Information
For additional information contact your local Fairchild
Semiconductor representative, or visit us at our web site
www.fairchildsemi.com.
AF36
10KΩ
2N7002
2N7002
Figure 6. Using VADJ to Generate VTT
12
REV. 1.0.6 6/26/01