FAN3268_11 Datasheet, PDF (12/16 Pages) Fairchild Semiconductor – 2A Low-Voltage PMOS-NMOS Bridge Driver

Layout and Connection Guidelines
The FAN3268 gate driver incorporates fast-reacting
input circuits, short propagation delays, and powerful
output stages capable of delivering current peaks over
2A to facilitate voltage transition times from under 10ns
to over 150ns. The following layout and connection
guidelines are strongly recommended:
 Keep high-current output and power ground paths
separate from logic and enable input signals and
signal ground paths. This is especially critical when
dealing with TTL-level logic thresholds at driver
inputs and enable pins.
 Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and surrounding
circuitry.
 If the inputs to a channel are not externally
connected, the internal 100k resistors indicated
on block diagrams command a low output (channel
A) or a high output (channel B). In noisy
environments, it may be necessary to tie inputs or
enables of an unused channel to VDD or GND
using short traces to prevent noise from causing
spurious output switching.
 Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
triggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts with long input, enable, or output leads. For
best results, make connections to all pins as short
and direct as possible.
 The turn-on and turn-off current paths should be
minimized.
Operational Waveforms
Figure 28 shows startup waveforms for non-inverting
channel A. At power-up, the driver output for channel A
remains low until the V_DD voltage reaches the UVLO turn-
on threshold, then OUTA operates in-phase with INA.
Figure 28. Non-Inverting Startup Waveforms
Figure 29 illustrates startup waveforms for inverting
channel B. At power-up, the driver output for channel B
is tied to V_DD through an internal 100kΩ resistor until the
V_DD voltage reaches the UVLO turn-on threshold, then
OUTB operates out of phase with INB.
Figure 29. Inverting Startup Waveforms
© 2009 Fairchild Semiconductor Corporation
FAN3268 • Rev. 1.0.1
12
www.fairchildsemi.com