FAN2106 Datasheet, PDF (12/14 Pages) Fairchild Semiconductor – TinyBuck 6A, 24V Input Integrated Synchronous Buck Regulator

MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
These two fault conditions are allowed to set the fault
latch at any time, including during soft-start.
Auto-Restart
After a fault, EN is discharged with 1µA to a 1.1V
threshold before the 800KΩ pull-up is restored. A new
soft-start cycle begins when EN charges above 1.35V.
Depending on the external circuit, the FAN2106 can be
provisioned to remain latched-off or automatically restart
after a fault.
Table 1. Fault / Restart Provisioning
EN pin
Controller / Restart State
Pull to GND OFF (disabled)
V_CC
Open
No restart – latched OFF
Immediate restart after fault
Cap to GND
New soft-start cycle after:
t_DELAY (msec) = 3.9 • C(nf)
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin to the VCC
pin or drive it with a logic gate to keep the 1µA current
sink from discharging EN to 1.1V.
Power-Saving Mode
The FAN2106 maintains high efficiency at light load by
changing to a discontinuous constant peak current,
power-saving mode (PSM).
The transition to power-saving mode occurs when the load
is <ΔI_L/2 for eight consecutive clock cycles.
In power-saving mode, a constant peak inductor current
(ΔI_LPSM) is generated each on-cycle. ΔI_LPSM is nominally
35% larger than PWM mode inductor ripple (ΔI_L).
During power-saving mode, the output is regulated to a
slightly higher value than its set point, since the current
pulse is triggered when FB crosses V_REF.
The IC is prevented from switching in the audible band.
If the FB pin has not dropped to V_REF within 40µsec of
the last pulse, the IC sinks current through the inductor
to initiate a new cycle.
Transition back to PWM mode is achieved when a load
transient causes the output voltage to drop 1.5% below
its regulation point.
1.88
Increasing Load
1.86
Decreasing Load
1.84
1.82
Forced PWM
1.80
1.78
0
1
2
3
4
5
6
Load (A)
Figure 24. Power-Saving Mode Regulation
(Using Figure 10 Circuit)
Power-saving mode operation is defeated by connecting
the PWM# pin to AGND, allowing only PWM operation.
The PWM# pin has a 1µA pull-down. If <0.6V is
detected, power-saving mode operation is disabled.
Figure 23. Fault Latch with Delayed Auto-Restart
PCB Layout
Over-Temperature Protection
The chip incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 150°C is reached. The IC is allowed to restart
when the die temperature falls below 125°C.
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when
V_OUT is out of regulation, as measured at the FB pin.
Thresholds are specified in the Electrical Specifications
section. PGOOD does not assert HIGH until the fault
latch is enabled (T1.0).
Figure 25. Recommended PCB Layout
© 2006 Fairchild Semiconductor Corporation
FAN2106 Rev. 1.0.1
12
www.fairchildsemi.com