FAN2106 Datasheet, PDF (10/14 Pages) Fairchild Semiconductor – TinyBuck 6A, 24V Input Integrated Synchronous Buck Regulator

Circuit Description
Application Note AN-6033 — FAN2106 Design Guide
includes a spreadsheet design aid to calculate external
component values and verify loop stability given the
following inputs:
ƒ Output voltage
ƒ Input voltage range
ƒ Maximum output load current
ƒ Maximum load transient current and maximum
allowable output drop during load transient
ƒ Maximum allowable output ripple
ƒ Desired switching frequency
Initialization
Once V_CC exceeds the UVLO threshold and EN is HIGH,
the IC checks for an open or shorted FB pin before
releasing the internal soft-start ramp (SS).
If R1 is open, the error amplifier output (COMP) is forced
LOW and no pulses are generated. After the SS ramp
times out (T1.0), an under-voltage latched fault occurs.
If the parallel combination of R1 and R_BIAS is ≤ 1KΩ, the
internal SS ramp is not released and the regulator does
not start.
Soft-Start
Once SS has charged to 0.8V (T0.8), the output voltage
is in regulation. Until SS reaches 1.0V (T1.0), the “Fault
Latch” and power-saving mode operations are inhibited.
To avoid skipping the soft-start cycle, it is necessary to
apply PVIN before V_CC reaches its UVLO threshold.
Soft-start time is a function of oscillator frequency.
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until SS
reaches 95% of V_REF (~0.76V). This prevents the
regulator from discharging the output and ensures that
inductor current does not "ratchet" up during the soft-
start cycle.
V_CC UVLO or toggling the EN pin discharges the SS and
resets the IC.
Bias Supply
The FAN2106 requires a 5V supply rail to bias the IC
and provide gate-drive energy. Connect a >1.0µf X5R or
X7R decoupling capacitor between VCC and PGND.
Since V_CC is used to drive the internal MOSFET gates,
supply current is frequency and voltage dependent.
Approximate V_CC current (I_CC) can be calculated using:
I_{CC(mA )}
=
4.58
+
[( ^{VCC −}
227
5
+
0.013) •
(F
− 128)]
EQ. 1
where frequency (F) is expressed in KHz.
Setting the Output Voltage
The output voltage of the regulator can be set from 0.8V
to 90% of V_IN by an external resistor divider (R1 and
R_BIAS in Figure 1).
The internal reference is 0.8V with 650nA, sourced from
the FB pin to ensure that, if the pin is open, the regulator
does not start.
The external resistor divider is calculated using:
0.8V ₌ V_OUT − 0.8V _{− 650nA}
R_BIAS
R1
EQ. 2
Connect R_BIAS between FB and AGND.
To minimize noise pickup on the FB node, the values of
R1 and R_BIAS should be selected to provide a minimum
parallel impedance of 1KΩ.
Figure 20. Soft-Start Timing Diagram
Setting the Frequency
Oscillator frequency is determined by an external resistor,
R_T, connected between the R(T) pin and AGND:
F_{(KHz )}
=
(65
10⁶
• R_T )
+ 135
EQ. 3
where R_T is expressed in KΩ.
R_{T(KΩ )}
=
(10⁶
/ F) − 135
65
EQ. 4
where frequency (F) is expressed in KHz.
The regulator can not start if R_T is left open.
© 2006 Fairchild Semiconductor Corporation
FAN2106 Rev. 1.0.1
10
www.fairchildsemi.com