FAN2103_12 Datasheet, PDF (12/14 Pages) Fairchild Semiconductor – 3 A, 24 V Input, Integrated Synchronous Buck Regulator

Because the FAN2103 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
R_RAMP provides feedforward compensation for changes
in V_IN. With a fixed R_RAMP value, the modulator gain
increases as V_IN is reduced, which could make it difficult
to compensate the loop. For designs with low input
voltages (3 V to 6.5 V), it is recommended that a
separate R_RAMP and the compensation component
values are used as compared to designs with V_IN
between 6.5 V and 24 V.
Protection
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions.
An internal “Fault Latch” is set for any fault intended to
shut down the IC. When the fault latch is set, the IC
discharges V_OUT by enhancing the low-side MOSFET
until FB<0.25 V. The MOSFET is not turned on again
unless FB>0.5 V. This behavior discharges the output
without causing undershoot (negative output voltage).
Table 1. Fault / Restart Provisioning
EN pin
Controller / Restart State
Pull to GND OFF (disabled)
V_CC
No restart – latched OFF (after V_CC
comes up)
Open
Immediate restart after fault
Cap to GND
New soft-start cycle after:
t_DELAY (ms) = 3.9 • C(nf)
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin to the VCC pin
or pull it high after V_CC comes up with a logic gate to keep
the 1 µA current sink from discharging EN to 1.1 V.
0.25/0.5V
FB
FAULT
PWM LATCH
PWM GATE
DRIVE
Figure 24. Latched Fault Response
Under-Voltage Shutdown
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This fault is prevented from
setting the fault latch during soft-start.
Over-Voltage Protection / Shutdown
If FB exceeds 115% • V_REF for two consecutive clock
cycles, the fault latch is set and shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
The two fault protection circuits above are active all the
time, including during soft-start.
Auto-Restart
After a fault, EN is discharged with 1 µA to a 1.1 V
threshold before the 800 KΩ pull-up is restored. A new
soft-start cycle begins when EN charges above 1.35 V.
Depending on the external circuit, the FAN2103 can be
provisioned to remain latched-off or automatically restart
after a fault.
Figure 25. Fault Latch with Delayed Auto-Restart
Over-Temperature Protection
FAN2103 incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 160°C is reached. The IC is allowed to restart
when the die temperature falls below 130°C.
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when
V_OUT is out of regulation, as measured at the FB pin
(thresholds are specified in the Electrical Specifications
section). PGOOD does not assert HIGH until the fault
latch is enabled (T1.0).
PCB Layout
Figure 26. Recommended PCB Layout
© 2007 Fairchild Semiconductor Corporation
FAN2103 • Rev. 1.0.8
12
www.fairchildsemi.com