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FAN2103_12 Datasheet, PDF (11/14 Pages) Fairchild Semiconductor – 3 A, 24 V Input, Integrated Synchronous Buck Regulator
Calculating the Inductor Value
Typically the inductor is set for a ripple current (ΔIL) of
10% to 35% of the maximum DC load. Regulators
requiring fast transient response use a value on the high
side of this range, while regulators that require very low
output ripple and/or use high-ESR capacitors restrict
allowable ripple current:
ΔIL = VOUT • (1 - D)
(5)
L•f
where f is the oscillator frequency and:
L
=
VOUT • (1
ΔIL • f
-
D)
(6)
Setting the Ramp Resistor Value
The internal ramp voltage excursion (∆VRAMP) during tON
should be set to 0.6 V. RRAMP is approximately:
RRAMP(KΩ )
=
(VIN − 1.8) • VOUT
18x10−6 • VIN • f
−2
(7)
where frequency (f) is expressed in KHz.
Setting the Current Limit
The current limit system involves two comparators. The
MAX ILIMIT comparator is used with a VILIM fixed-voltage
reference and represents the maximum current limit
allowable. This reference voltage is temperature
compensated to reflect the RDSON variation of the low-
side MOSFET. The ADJUST ILIMIT comparator is used
where the current limit needs to be set lower than the
VILIM fixed reference. The 10 µA current source does not
track the RDSON changes over temperature, so change is
added into the equations for calculating the ADJUST
ILIMIT comparator reference voltage, as is shown below.
Figure 22 shows a simplified schematic of the over-
current system.
RAMP
VERR
PWM
+ COMP
_
PWM
VCC
10µA
ILIM
RILIM
VILIM
MAX
+ ILIMIT
_
ADJUST
+ ILIMIT
_
ILIMTRIP
VRILIM = 10µA*RILIM
(8)
To calculate RILIM:
RILIM = VRILIM/ 10µA
(9)
The voltage VRILIM is made up of two components, VBOT
(which relates to the current through the low-side
MOSFET) and VRMPEAK (which relates to the peak
current through the inductor). Combining those two
voltage terms results in:
RILIM = (VBOT + VRMPEAK)/ 10µA
(10)
RILIM = {0.96 + (ILOAD * RDSON *KT*8)} +
{D*(VIN – 1.8)/(fSW*0.03*RRAMP)}/10µA
(11)
where:
VBOT = 0.96 + (ILOAD * RDSON *KT*8);
VRMPEAK = D*(VIN – 1.8)/(fSW*0.03*RRAMP);
ILOAD = the desired maximum load current;
RDSON = the nominal RDSON of the low-side MOSFET;
KT = the normalized temperature coefficient for the
low-side MOSFET (on datasheet graph);
D = VOUT/VIN duty cycle;
fSW = Clock frequency in kHz; and
RRAMP = chosen ramp resistor value in kΩ.
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to the Auto-Restart
section).
The over-current protection fault latch is active during
the soft-start cycle. Use 1% resistor for RILIM.
Loop Compensation
The loop is compensated using a feedback network
around the error amplifier. Figure 23 shows a complete
Type-3 compensation network. Type-2 compensation
eliminates R3 and C3.
Figure 22. Current-Limit System Schematic
Since the ILIM voltage is set by a 10 µA current source
into the RILIM resistor, the basic equation for setting the
reference voltage is:
Figure 23. Compensation Network
© 2007 Fairchild Semiconductor Corporation
FAN2103 • Rev. 1.0.8
11
www.fairchildsemi.com