FAN2103 Datasheet, PDF (12/14 Pages) Fairchild Semiconductor – 3A, 24V Input Integrated Synchronous Buck Regulator

Table 1. Fault / Restart Provisioning
EN pin
Controller / Restart State
Pull to GND OFF (disabled)
VCC
Open
No restart – latched OFF
Immediate restart after fault
Cap to GND
New soft-start cycle after:
tDELAY (msec) = 3.9 • C(nf)
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin to the VCC
pin or drive it with a logic gate to keep the 1µA current
sink from discharging EN to 1.1V.
During power-saving mode, the output is regulated to a
slightly higher value than its set point, since the current
pulse is triggered when FB crosses VREF.
The IC is prevented from switching in the audible band.
If the FB pin has not dropped to VREF within 40µs of the
last pulse, the IC sinks current through the inductor to
initiate a new cycle.
Transition back to PWM mode is achieved when a load
transient causes the output voltage to drop 1.5% below
its regulation point.
1.85
1.84
1.83
1.82
1.81
1.8
PWM to PSM
Transition
1.79
1.78
0
0.25
0.5
0.75
PSM to PWM
PWM to PSM
PSM to PWM
Transition
1
1.25
1.5
Figure 24. Fault Latch with Delayed Auto-Restart
Over-Temperature Protection
FAN2103 incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 160°C is reached. The IC is allowed to restart
when the die temperature falls below 130°C.
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW
when VOUT is out of regulation, as measured at the FB
pin (thresholds are specified in the Electrical
Specifications section). PGOOD does not assert HIGH
until the fault latch is enabled (T1.0).
Power-Saving Mode
The FAN2103 maintains high efficiency at light load by
changing to a discontinuous, constant peak current,
power-saving mode (PSM).
The transition to power-saving mode occurs when the load
is <ΔIL/2 for eight consecutive clock cycles.
In power-saving mode, a constant-peak inductor current
(ΔILPSM) is generated each on-cycle. ΔILPSM is nominally
85% larger than PWM-mode inductor ripple (ΔIL).
Figure 25. Power-Saving Mode Regulation
(Using Figure 10 Circuit)
Power-saving mode operation can be disabled by
connecting the PWM# pin to AGND, allowing only PWM
operation. The PWM# pin has a 1µA pull-down. If <0.6V
is detected, power-saving mode operation is disabled.
PCB Layout
Figure 26. Recommended PCB Layout
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
12
www.fairchildsemi.com