FAN2103 Datasheet, PDF (10/14 Pages) Fairchild Semiconductor – 3A, 24V Input Integrated Synchronous Buck Regulator

Circuit Description
Initialization
Once VCC exceeds the UVLO threshold and EN is
HIGH, the IC checks for an open or shorted FB pin
before releasing the internal soft-start ramp (SS).
If R1 is open, the error amplifier output (COMP) is forced
LOW and no pulses are generated. After the SS ramp
times out (T1.0), an under-voltage latched fault occurs.
If the parallel combination of R1 and RBIAS is ≤ 1KΩ, the
internal SS ramp is not released and the regulator does
not start.
Soft-Start
Once SS has charged to 0.8V (T0.8), the output voltage
is in regulation. Until SS reaches 1.0V (T1.0), the “Fault
Latch” and power-saving mode operations are inhibited.
To avoid skipping the soft-start cycle, it is necessary to
apply VIN before VCC reaches its UVLO threshold.
Soft-start time is a function of oscillator frequency.
EN
1.35V
2400 CLKs
0.8V
FB
1. 0V
0. 8V
F ault
La t c h
Enable
SS
3200 CLKs
T0.8
4000 CLKs
T1.0
Figure 21. Soft-Start Timing Diagram
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until SS
reaches 95% of VREF (~0.76V). This helps the regulator
start against pre-biased outputs and ensures that
inductor current does not "ratchet" up during the soft-
start cycle.
VCC UVLO or toggling the EN pin discharges the SS and
resets the IC.
Bias Supply
The FAN2103 requires a 5V supply rail to bias the IC
and provide gate-drive energy and controller power.
Connect a >1.0µf X5R or X7R decoupling capacitor
between VCC and PGND. Whenever EN pin is pulled
up to VCC, the 5V supply connected to VCC should be
turned ON after VIN comes up. If the power supply is
turned ON using EN pin with an external control after
VCC and VIN come up, the VCC and VIN power
sequencing is not relevant.
Since VCC is used to drive the internal MOSFET gates,
supply current is frequency and voltage dependent.
Approximate VCC current (ICC) can be calculated using:
I_{CC(mA )}
=
4.58
+
[(
V_CC −
227
5
+
0.013)
• (F
− 128)]
(1)
where frequency (F) is expressed in KHz.
Setting the Output Voltage
The output voltage of the regulator can be set from 0.8V
to ~90% of VIN by an external resistor divider (R1 and
RBIAS in Figure 1).
The internal reference is 0.8V with 650nA, sourced from
the FB pin to ensure that if the pin is open, the regulator
does not start.
The external resistor divider is calculated using:
0.8V ₌ V_OUT − 0.8V _{+ 650nA}
(2)
R_BIAS
R1
Connect RBIAS between FB and AGND.
To minimize noise on the FB node, the values of R1
and RBIAS should be selected to provide a minimum
parallel impedance of 1KΩ.
Setting the Frequency
Oscillator frequency is determined by an external resistor,
RT, connected between the R(T) pin and AGND:
F_{(KHz )}
=
(65
10⁶
• R_T )
+ 135
(3)
where RT is expressed in KΩ.
R_{T(KΩ )}
=
(10⁶
/ F) − 135
65
(4)
where frequency (F) is expressed in KHz.
The regulator does not start if RT is left open.
Calculating the Inductor Value
Typically the inductor is set for a ripple current (ΔIL) of
10% to 35% of the maximum DC load. Regulators
requiring fast transient response use a value on the
high side of this range, while regulators that require very
low output ripple and/or use high-ESR capacitors
restrict allowable ripple current:
ΔIL = ^{VOUT • (1- D)}
(5)
L •F
where F is the oscillator frequency, and
L = ^{VOUT • (1- D)}
(6)
ΔIL • F
The selection of inductor influences the entry into
power-saving mode. Consider minimum and maximum
load conditions before inductor selection.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
10
www.fairchildsemi.com