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FOD260L Datasheet, PDF (11/19 Pages) Fairchild Semiconductor – LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
Package Dimensions (Continued)
SMT
Surface Mount – 0.3" Lead Spacing (Option S)
9.40–9.91
(1.78)
Pin 1
(2.54)
6.35–6.86
(7.49)
(10.54)
(1.54)
3.68–3.94
5.08
MAX
0.51 MIN
2.54 BSC
1.14–1.78
(0.78)
(0.41–0.56)
(0.76)
Recommended Land Pattern
0.20–0.40
0.40 MIN
Both sides
8.00 MIN
10.30 MAX
Surface Mount – 0.4" Lead Spacing (Option TS)
9.40–9.91
1.50
(1.78)
ø1.00 TYP
(2.54)
(1.54)
6.35–6.86
(9.96)
(13.00)
(0.76)
Recommended Land Pattern
3.68–3.94
1.14–1.78
7.62 TYP
5.08
MAX
0.20–0.40
0.51 MIN
2.54 TYP
(0.78)
0.40 MIN
Both sides
10.16
Note:
12.60 MAX
1. All dimensions are in millimeters.
2. Dimensions are exclusive of burrs, mold fash, and tie bar extrusion.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2008 Fairchild Semiconductor Corporation
FOD060L, FOD260L Rev. 1.0.5
11
www.fairchildsemi.com