FAN5109 Datasheet, PDF (10/13 Pages) Fairchild Semiconductor – Dual Bootstrapped 12V MOSFET Driver

Circuit Description
The FAN5109 is a driver optimized for driving N-channel
MOSFETs in a synchronous buck converter topology. A
single PWM input signal is all that is required to properly
drive the high-side and the low-side MOSFETs.
For a more detailed description of the FAN5109 and its
features, refer to the Typical Application Diagram (Figure 1)
and Functional Block Diagram (Figure 3).
Low-Side Driver
The FAN5109’s low-side driver (LDRV) is designed to
drive ground referenced low R_DS(on) N-channel
MOSFETs. The bias for LDRV is internally connected
between V_CC and PGND. When the driver is enabled, the
driver’s output is 180° out of phase with the PWM input.
When the FAN5109 is disabled (OD = 0V), LDRV is held
low.
High-Side Driver
The FAN5109’s high-side driver (HDRV) is designed to
drive a floating N-channel MOSFET. The bias voltage for
the high-side driver is developed by a bootstrap supply
circuit, consisting of an external diode and bootstrap
capacitor (C_BOOT) .
During start-up, SW is held at PGND, allowing C_BOOT to
charge to V_CC through the diode. When the PWM input
goes high, HDRV will begin to charge the high-side
MOSFET’s gate (Q1). During this transition, charge is
transferred from C_BOOT to Q1’s gate. As Q1 turns on,
SW rises to V_IN, forcing the BOOT pin to V_IN +V_C(BOOT),
which provides sufficient V_GS enhancement for Q1.
To complete the switching cycle, Q1 is turned off by pull-
ing HDRV to SW. C_BOOT is then recharged to V_CC when
SW falls to PGND.
HDRV output is in phase with the PWM input. When the
driver is disabled, the high-side gate is held low.
Adaptive Gate Drive Circuit
The FAN5109 embodies an advanced design that
ensures minimum MOSFET dead-time while eliminating
potential shoot-through (cross-conduction) currents. It
senses the state of the MOSFETs and adjusts the gate
drive, adaptively, to ensure they do not conduct simulta-
neously. Refer to "Gate Drive Rise and Fall Times" wave-
forms on page 7 for the relevant timing information.
To prevent overlap during the low-to-high switching tran-
sition (Q2 OFF to Q1 ON), the adaptive circuitry monitors
the voltage at the LDRV pin. When the PWM signal goes
HIGH, Q2 will begin to turn OFF after some propagation
delay as defined by t_pdl(LDRV) parameter. Once the LDRV
pin is discharged below ~1.3V, Q1 begins to turn ON
after adaptive delay t_pdh(HDRV).
To preclude overlap during the high-to-low transition (Q1
OFF to Q2 ON), the adaptive circuitry monitors the volt-
age at the SW pin. When the PWM signal goes LOW, Q1
will begin to turn OFF after some propagation delay
(t_pdl(HDRV)). Once the SW pin falls below ~V_CC/3, Q2
begins to turn ON after an adaptive delay t_pdh(LDRV).
Additionally, V_GS of Q1 is monitored. When V_GS(Q1) is
discharged below ~1.3V, a secondary adaptive delay is
initiated, which results in Q2 being driven ON after
t_pdh(LDF), regardless of the SW state. This function is
implemented to ensure C_BOOT is recharged after each
switching cycle, particularly for cases where the power
convertor is sinking current and the SW voltage does not
fall below the V_CC/3 adaptive threshold. Secondary delay
t_pdh(LDF) is longer than t_pdh(LDRV).
Application Information
Supply Capacitor Selection
For the supply input (V_CC) of the FAN5109, a local
ceramic bypass capacitor is recommended to reduce the
noise and to supply the peak current. Use at least a 1µF,
X7R or X5R capacitor. Keep this capacitor close to the
FAN5109’s V_CC and PGND pins.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C_BOOT) and an external diode, as shown in Figure 1.
These components should be selected after the high-
side MOSFET has been chosen. The required capaci-
tance is determined using the following equation:
C_BOOT = _∆-----V---Q-_B---_OG----_O----_T-
(1)
where Q_G is the total gate charge of the high-side
MOSFET, and ∆V_BOOT is the voltage droop allowed on
the high-side MOSFET drive. For example, the Q_G of the
FDD6696 MOSFET is about 35nC @ 12V_GS. For an
allowed droop of ~300mV, the required bootstrap capaci-
tance is 100nF. A good quality ceramic capacitor must be
used.
The average diode forward current, I_F(AVG), can be esti-
mated by:
I_F(AVG) = Q_GATE × F_SW
(2)
where F_SW is the switching frequency of the controller.
The peak surge current rating of the diode should be
checked in-circuit, since this is dependent on the equiva-
lent impedance of the entire bootstrap circuit, including
the PCB traces.
Layout Considerations
Use the following general guidelines when designing
printed circuit boards (see Figure 7 on the next page):
1. Trace out the high-current paths and use short, wide
(>25 mil) traces to make these connections.
2. Connect the PGND pin of the FAN5109 as close as
possible to the source of the lower MOSFET.
10
FAN5109 Rev. 1.0.4
www.fairchildsemi.com