ES25P40 Datasheet, PDF (15/35 Pages) Excel Semiconductor Inc. – 4Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface

ADVANCED INFORMATION
EE SS II
Excel Semiconductor inc.
CS#
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
Instruction
24-Bit Address
0 0 0 0 0 0 1 1 ^{23 22 21}
MSB
High Impedance
3210
Data Out 1
Data Out 2
7 6 5 43 2 1 07
MSB
Figure 9. Read Data Bytes (READ) Instruction Sequence
Read Data Bytes (READ)
The READ instruction reads the memory at the
specified SCK frequency (fsck) with a maximum
speed of 40MHz.
The device is first selected by driving Chip Select
(CS#) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23 - A0), each bit being latched-in during
the rising edge of Serial Clock (SCK). Then the
memory contents, at the address, are shifted out on
Serial Data Output (SO), each bit being shifted out,
at a frequency fsck, during the falling edge of Serial
Clock (SCK).
The instruction sequence is shown in Figure 9. The
first byte addressed can be at any location. The
address automatically increments to the next higher
address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single
Read Data Bytes (READ) instruction. When the
highest address is reached, the address counter
rolls over to 00000h, allowing the read sequence to
be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (CS#) High. Chip Select
(CS#) can be driven High at any time during data
output. Any Read Data Bytes (READ) instruction,
while a Program, Erase, or Write cycle is in
progress, is rejected without having any effect on the
cycle that is in progress.
Read Data Bytes at Higher Speed
(FAST_ READ)
The FAST_READ instruction reads the memory at
the specified SCK frequency (fsck) with a maximum
speed of 75 MHz. The device is first selected by
driving Chip Select (CS#) Low. The instruction code
for FAST_READ instruction is followed by a 3-byte
address (A23 - A0) and a dummy byte, each bit
being latched in during the rising edge of Serial
Clock (SCK). Then the memory contents, at that
address, are shifted out on Serial Data Output
(SO), each bit being shifted out. at a maximum fre-
quency Fsck, during the falling edge of Serial Clock
(SCK).
The instruction sequence is shown in Figure 10.
The first byte addressed can be at any location.
The address automatically increments to the next
higher address after each byte of data is shifted
out. The whole memory can, therefore, be read with
a single FAST_READ instruction.
When the highest address is reached, the address
counter rolls over to 00000h, allowing the read
sequence to be continued indefinitely
The FAST_READ instruction is terminated by driv-
ing Chip Select (CS#) High. Chip Select (CS#) can
be driven High at any time during data output. Any
FAST_READ instruction, while an Erase, Program
or Write cycle is in progress, is rejected without
having any effects on the cycle that is in progress.
ES25P40
15
Rev. 0D May 11 , 2006