XRD9814 Datasheet, PDF (9/53 Pages) Exar Corporation – 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors

XRD9814/9816
ELECTRICAL CHARACTERISTICS (CONT’D)
AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter
Symbol Min
Typ
Max
Unit
Conditions
TIMING SPECIFICATIONS
ADCCLK Pulse Width
taclk 66.5
ns
BSAMP falling edge delay from tbfcr 10
ns
rising ADCCLK
BSAMP falling edge to VSAMP tbvf
70
ns
falling edge.
ADCCLK Period (1 Ch. Mode) tcp1 166
ns
ADCCLK Period (3 Ch. Mode) tcp3 133
ns
1-Channel Conversion Period
tcr1 166
ns
3-Channel Conversion Period
tcr3 400
ns
BSAMP Pulse Width
tpwb 30
ns
VSAMP Pulse Width
tpwv 30
ns
VSAMP falling edge to BSAMP tvbf
70
falling edge.
VSAMP falling edge delay from tvfcr 30
rising ADCCLK.
VSAMP falling edge delay
tvfcr 70
from rising ADCCLK
PGA Settling Time
tstl
70
Aperture Delay
tap
5
ns
ns
All modes except 1-Channel
S/H
ns
1-Channel S/H, Config
REG #1, PB2=1, PB7=1
ns
ns
VSAMP TIMING OPTION #1
VSAMP rising edge delay from tvrcf 15
falling ADCCLK (Note 1)
ns
tvrcr is not required, Config
REG #1, PB0=0
VSAMP TIMING OPTION #2
VSAMP rising edge delay from tvrcr 15
rising ADCCLK (Note 1)
ns
tvrcf is not required, Config
REG # 1, PB0=1
WRITE SPECIFICATIONS
Data Setup Time
tds
15
ns
Data Hold Time
tdh
15
ns
Load Setup Time
tlcs
15
ns
Load Hold Time
tlch
15
ns
Load Pulse Width
tplw 25
ns
Note 1: VSAMP Timing Option #2 allows additional timing flexibility by allowing the rising edge of VSAMP to occur
approximately one-half ADCCLK period earlier than Option #1. Option #2 is only available in 3-Channel
Operation (PB4=0, PB3=0, Configuration Register #1).
Rev. 1.00
9