XRD9814 Datasheet, PDF (19/53 Pages) Exar Corporation – 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors

XRD9814/9816
3-Channel CIS/Sample and Hold Mode
The XRD9814/9816 also supports operation for Con-
tact Image Sensor (CIS) and S/H applications. The
green channel is synchronized on the rising edge of the
first ADCCLK after the falling edge of VSAMP.
For DC coupled inputs the reference clamp and input
buffer should be disabled and input polarity should be
set to 1 (non-inverting). In this mode of operation the
BSAMP input is connected to DGND and input sam-
pling occurs on the falling edge of VSAMP.
When using AC coupled inputs the coupling capacitor
must be clamped to the required common-mode input
voltage when the signal source output is at a reference
level. This can be accomplished by enabling the S/H
Line clamp mode in configuration register 1 and clamp-
ing the input capacitor to the internal clamp voltage at
the beginning of each line via the LCLMP input. The
required width of the LCLMP signal is dependent on the
value of the coupling capacitor, XRD9814/9816 clamp
resistance, source output resistance and desired ac-
curacy. This is explained further in Coupling Capacitor
Requirements. If AC coupling is used the input buffer
(configuration register 1) must be enabled to eliminate
input-bias current errors inherent to the sampling pro-
cess. The input buffer is not required or recommended
in DC coupled applications.
1-Channel CIS/ Sample and Hold Mode
The 1-channel CIS S/H mode allows high-speed
acquisition and processing of a single channel. The
timing, clamp and buffer configurations are similar to
the 3-channel mode with the exception that VSAMP
timing option #2 is not supported. To select a single
channel input the color bits of configuration register 1
must be set to the appropriate value. The A/D input will
begin to track the selected color input on the next
positive edge of ADCCLK. If the configuration is
toggled from single color to 3-channel mode, RGB
scanning will not occur until the circuit is
resynchronized.
Power Supplies and Digital I/O
The XRD9814/9816 utilizes separate analog and
digital power supplies. All digital I/O pins are 3V/5V
compatible and allow easy interfacing to external
digital ASICs. For single supply systems the analog
and digital supply pins can be separately connected
and bypassed to reduce noise coupling from digital to
analog circuits.
Coupling Capacitor Requirements
The size of the external coupling capacitors depends
on a number of items including the clamp mode, pixel
rate, channel gain, black-level variation and system
accuracy requirements. The major limitation for each
clamp mode is shown below:
Pixel Clamp
(Buffer
Disabled)
CDS Mode
Black level
pixel-pixel
variation
S/H Mode
Not Applicable
Initial charging
Line Clamp
(Buffer
Enabled)
Initial charging
Capacitor droop
(common-mode
range)
Initial charging
Capacitor droop
range)
(accuracy error)
Table 5. Coupling Capacitor Limitation
Rev. 1.00
19